How to use a While-Loop in VHDL

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  • Опубліковано 11 січ 2025

КОМЕНТАРІ • 12

  • @sakuranooka
    @sakuranooka 3 роки тому +2

    This is a comment re the first 5 videos of the course. It's a nice introduction thank you. However, I was wondering whether it was a good idea to introduce VHDL by emphasizing the similarities between VHDL and sequential, algorithmic languages. Of course it simplifies the first steps for a beginner, but at a later stage it might make the learning process more difficult because people are stuck in this sequential paradigm while the essential part of VHDL, as a hardware *description* language, is non-sequential. Just my two cents...

    • @VHDLwhiz
      @VHDLwhiz  3 роки тому

      I've always thought of VHDL as a parallel programming language that's well suited for modeling digital hardware. But I welcome other opinions.
      The free VHDL course that this video belongs to only uses simulation, and doesn't talk much about the hardware. I've developed a new course that teaches the same VHDL constructs in the context of the real FPGA project.
      Those who are interested can check out the FPGA and VHDL Fast-Track course here:
      academy.vhdlwhiz.com/fast-track

  • @christianjensen7699
    @christianjensen7699 3 роки тому +2

    For most of us C programmers it would be useful to discuss sizes and such when implementing variables. What is the size of i? is it an int, or uint8_t, or int_8_t? Can it just be overrun like a ptr to an array or does it recycle back to 0? what if you incremented by 10,000?

    • @VHDLwhiz
      @VHDLwhiz  3 роки тому

      VHDL's built-in integer type is 32-bit prior to VHDL-2019 and 64-bit from VHDL-2019 (not widely used yet). They will overflow like int32 and int64 in C. Later in the "How to use Signed and Unsigned in VHDL" lesson in this tutorial series, you will learn how to create integers of any length in VHDL.

  • @hojiafzal9559
    @hojiafzal9559 4 місяці тому

    Hi Whiz, after I edit my file in Notepad++, modelsim does not update its local copy consistently. For a while it did ask me if I wanted to update the file, but that has stopped. How can I change this behaviour so after I save my changes in Notepad++, the modelsim version consistently reflects those changes, or at least ask me if I want to update the file?
    Thanks very much

    • @VHDLwhiz
      @VHDLwhiz  4 місяці тому

      I usually close the editor in ModelSim and only use the external editor. Although, I've changed from Notepad++ to VSCode lately. Check out the "VHDLwhiz" extension for VSCode. I only use the Questa/ModelSim editor for debugging and placing breakpoints.
      I'm not sure if there's a way to make it reflect the changes faster. It's supposed to ask if you want to update the files you have open in the simulator editor. Sounds like there's something wrong. But, as I said, you don't really need the Questa editor except for placing breakpoints.

    • @hojiafzal9559
      @hojiafzal9559 4 місяці тому

      @@VHDLwhiz
      Dear Whiz, I can't thank you enough for responding so promptly!
      I actually found a solution to my issue: from ModelSim INTEL FPGA STARTER EDITION 10.5b/Tools/Edit Preferences/By Name/Find you can search for "reload" and set "AutoReloadModifiedFiles" to 1.
      I wanted to update my inquiry here, but didn't think you would respond so quickly.
      Thank you so much!

  • @DivyaSree-410
    @DivyaSree-410 6 місяців тому

    sir iam not getting to open output window in modelsim .i have draged window but it is not displaying the output what should do

  • @artunsaday6391
    @artunsaday6391 6 років тому +2

    Why didn't we declared i in the for loop?

    • @VHDLwhiz
      @VHDLwhiz  6 років тому +2

      Artun Saday Because it is implicitly declared for us in the for-loop. You cannot have a for-loop without a variable. A while-loop doesn't have this kind of index variable.

    • @artunsaday6391
      @artunsaday6391 6 років тому

      Thanks a lot!

  • @kindjupiter
    @kindjupiter 7 років тому +1

    thank you sir