Breaking Clock Speed Limits - TTL Computer in Beast Mode
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- Опубліковано 11 вер 2024
- I explore the clock speed limits of TTL computers. I specifically overclock the 'Minimal CPU' successfully to 8.3MHz. Do you know of any faster-clocked DIY TTL computer? Write it in the comments!
Minimal CPU System:
github.com/slu...
User Manual and Reference (Google Docs):
docs.google.co...
Discussion Board:
minimal-cpu-sy...
It shows that speeding up the clock rate is not just down to changing the chips for a faster series, you can get an improvement from optimising the clock signal. I love your explanation why it can run faster just with an asymmetrical clock. Optimisation can be difficult but very worthwhile. Maybe your next step can be to lower the number of micro-code steps but keep the chip count to the minimum and the CPU's functionality the same.
Hi David, good to see you here and thanks for your kind words :-) In fact, the number of microcode steps needed for various instructions is already creeping downwards with version 1.6 (see the Minimal Online Manual). It's funny, almost like exploring a cave, one little breakthrough leads to a whole new hall - just so happened this morning. This project never ends ;-)
@@slu467 hey i love your channel! Was wondering, are there any drawbacks to having a signal that is not square? Are reliability or other factors affected?
@@ank2000 I can't answer your question in general. It very much depends on the actual circuit. In any case I've made the experience that once you squeeze out maximum performance things tend to get hairy...😄
I read 'Digital Computer Electronics' by Paul Malvino in school back in the '80s. Time to dig it out of storage since it now goes for $100-150. Great book indeed. I'll never forget the SAP and its heart, the Ring Counter...
Most fascinating experiments and results. Well done!
Thanks a lot!
Very cool! Advanced shottky (AS) ICs are the fastest and most robust in my experience. They tend to get very warm, though.
The "HC" ICs you are using should be around 10ns like typical "LS" type ICs. Going to "ALS" will reduce the delay to around 4ns and going to "AS" will further reduce it to 1.5 - 2ns.
Sometimes i have used 74S ICs for flaky circuits. They are extremely robust and will output a lot more mA on the pins. They are more resistant to RF and will hardly ever go bad despite mishandling. The 'original' Shottky ICs have a high internal resistance and are very power hungry. They will most likely not be usable in your setup.
Very nice work, getting above 4MHZ is a real challenge, especially on breadboard!
The PJ5CPU I'm working on runs at 4MHZ, but gives 4MIPS (TTL based), it does have a display (graphic and text) and RAM.
Hi Paula, I am following your design steps every now and then. Very impressive, feature-rich and efficient - and quite the opposite of what I am doing ;-) My CPU is simplistic and inefficient. At 8MHz it's just above 1MIPS. But it's only 39 TTL chips. I am also working on a full "home computer", with VGA and PS2. We'll see... currently it's 61 ICs in total ;-)
@@slu467 you design is wonderful, it's incredible how much you've got from such few chips.
Agreed the two are very different design philosophies, I very much enjoy your videos
@@PaulasTechStuff Thanks a lot for keeping me motivated :-) My next "upgrade" (actually it's going to be a real 2.0) will be a full home computer with 64K, VRAM, VGA out and PS/2 in, UART, expansion port. 8MHz is the entry card for generating VGA on the fly efficiently and with only *very* few chips :-) I am currently homing in on 61 chips for the whole deal.
@@slu467 I look forward to seeing this, 61 is very minimal!
8 MHz?!?! On a breadoard?!?! "impossible"!!!! ;)
I've only been flowing you and James Sharman ..... interesting that you've mentioned a few more TTL CPUs in the outro... I'll have to see if I can find them later.
Impressive demonstration, you can also use a PLL IC locked at 1Mhz and dynamically adjust clock speed using a latch.
Cheers ✨✨
I think might be time to write some new test games that push the hardware a bit harder! That's some amazing improvements you have made in the timing.
Hi Aaron, good to see you here again :-) as you can tell I'm kind of getting obsessed with this whole thing. Every few months I got drawn into it again - and each time a new and interesting door opens... btw, I am working on a new 'Minimal' rogue-like game.
@@slu467 it's easy to get hooked quickly!
I just found your channel recently. I really like it. SAP-1 on steroids. I work at Takuma Denpa Kousen (Now part of Kagawa Kousen with Takamatsu Kousen merger) in the Electronic System Engineering Department. I have 6 students working on Seminar and Sotsuken in my laboratory. I am thinking about having one or two of the students build this and maybe have one of them build a PCB of it or do something together if you are interested. I have two students who are probably capable enough to do something together with this...Anyway, really like this channel and your Soundcloud works as well. I actually used to practice/play with the "Rock n Roll" bukatsu and perform together in at Denpsai but haven't done that for about 8 or 9 years.
I'd certainly very much enjoy your students engaging in my designs. My new and upcoming full Minimal 64 home computer (only 61 ICs with VGA and PS/2) might be interesting. It is running Space Invaders :-) Currently, I am working on the release video. Cheers!
The TTL C74-6502 runs at 20Mhz.
The "MyCpu" also runs at 8Mhz.
In the commercial sector the PA-RISC TS1 CPU runs at 8Mhz. It is however a 32-bit pipelined machine that had all the goodies.
C74-6502 is a naked CPU - doesn't count... and PA-RISC TS1 uses fast TTL chips... MyCPU however is pretty close... ;-) have to look into this project.
Interesting that HC parts tend to show a disappointing drop in speed at, say, 3.3v rather than 5v; and according to the datasheets, AHC are not significantly faster, just a couple of nanoseconds.
I'm working on an 8080 facsimile using flash/eeprom/whatever as the control logic - which is likely to be the speed limit. It's a lot more parallel though, I think, so the delays stack up as eeprom access time plus ALU delay plus a couple of other short delays. I'm trying to keep the clock symmetric so I can use the clock high phase as a time for ram to be accessed by video, 6502 style, so I doubt if I will be anywhere near your speed.
Keep up the good work!
i love your work. it bring me back to time that i start learn computer but more than that i knew i will create one and learn about it. waiting for PCB version. cheers.
1:00 that's a really nice logo
Haha, I love the graphic for maximum clock speeds at "two and a fraction Commodore 64s" xD
I do not want it nitpick, but 74HCxx are not TTL but CMOS digital chips.
I have an idea for a small CPU project where the only instruction is “Move”. I’d be curious to see your opinions on the basic design!
Sounds like dhrystone is in order
Watching this video again, i see you are using a 74 chip as 3.3->5v level converter? Nice
Which one exactly? 74HCT245
Hi Alex, I use 74HCTxx chips when logic levels are low (compared to 5V). Any input will do, e. g. 74HCT245 or 74HCT04 for inversion or... If you deal with slow-rising signals a Schmitt-Trigger might be useful, too (see 74HCT132). Cheers.
You have the basics of cycle timing analysis well illustrated, the only thing you are really missing is setup and hold time on your memories and registered devices, but for that information you would need to refer to data sheets of the parts. Really good job on noticing the usefulness of an asymmetric clock.
I think you a little misguided though in worrying about whether you are running the fastest clock rate for a TTL computer. I would promote rather the idea of the "efficiency" of your CPU architecture in terms of instruction rate or maybe instructions per cycle. Let me illustrate. Back in the day of 8051's and 68HC11's and 6502's, a lot of engineers were touting the 8051 running at 12 MHz (crystal) was faster than the 68HC11, yet it took 12 cycles to complete each instruction for an effective instruction rate of 1 MHz. The 'HC11 on the other hand was running with an 8MHz (crystal, 2MHz E-Clock) clock was almost twice as fast depending on the instruction mix. All the CPU's you've mentioned have varying instructions per cycle so a raw clock rate doesn't necessarily represent how fast the CPU can get work done.
I've been really enjoying your series on the Minimal CPU, takes me back Your ideas on CPU emulation in Python are really first rate and I am learning from. Thank you.
Hi Todd, thanks for this interesting information. You are right, looking at clock speed alone is not enough. The design of the 'Minimal' is not about efficiency (hence the name :-). In fact, it does pretty bad: Is needs about 8.18CPI (average clocks per instruction) while running the 'Min' interpreter (might not be representative, but that is a complex piece of code doing lots of look-ups and memory moving - so I took it as a quick 'benchmark'). That would be just above 1Mips @ 8.3MHz for the Minimal. Really no match for any decent pipelined CPU design - but the Minimal only need 39 TTL chips in total ;-)
I would switch to ECL.
I'd rather optimize the design and keep it accessible by using standard logic. But thanks for the hint. One often forgets that the FLASH and SRAM ICs have to keep up, too ;-)
How are you? I noticed that your video has not been updated for a long time.
Hi Denjhang, still alive ;-) I am about to release my "next thing" - the Minimal 64 Home Computer. It took me 8 months to develop ;-) but it's done now... and coming soon.
@@slu467 Oh exciting! I've been planning on building a Minimal CPU system, will wait for the Minimal 64. (Although the name does make the project sound like it's a tiny Commodore 64)
@@soupwizard Well, is has 64K of RAM 🙂but double the processing power of a C64. I am currently recording the audio for the first MINIMAL 64 video. Might go online in just a couple of days...
can you benchmark it using some real world algorithm? My TTL computer currently takes 2.3 seconds to find all 8 bit prime numbers. (@4mhz)
Hi Seb, I am not saying the Minimal CPU is *efficient* - this video is just going for clock speed alone. See the Minimal Reference Manual for a benchmark.
@@slu467 mine isn't efficient either, but I'd like to know how it compares to other minimalistic designs.
@@SebGreen And if you're taking it to extremes, against less minimalistic designs like 8080, 6502, 6800... (oh the days of my youth :)
With the temperature change the propagation delay and transition time will also change...
Won't it break the stability? The idea of making clock not 50% duty cycle is brilliant, but i think for pcb MINIMAL design it's better to do a proper generator based on shift register?
Hi Alex, it probably won't run under space conditions ;-) I now use an even simpler clock pulse. See my updated schematics on GitHub ;-) Now running at 8.6MHz.
I was playing with inverters which give a 5ns delay and flip the phase and rippling a clock through it.
I also used a nand chip to take 2 clocks and generate a strobe for mem write.
The chips I'm using need around 45ns write signal and 5ns either side of address stability.
So my strobe comes along goes low briefly and then high. Then I have a couple delayed phase which goes high which I can jumper to latch the registers and instructions.
I'm not running very fast yet as still debugging but can experiment with shortening the strobe for mem write stability then moving the other phases closer and closer to the end of mem write.
Once I've done that I can measure the propagation time from instruction being latched to a stable state. Then start to ramp up the clock to remove the unneeded delay time before next write strobe.
I won't hit 8mhz as my address lines go into another sram to do a simple memory paging system to then output the physical address. Similar to magic one.
I've gone for a higher IPC design where most instructions are 2 clocks fetch and execute. To make up for the larger propagation time.
I was reading about magic 1 swapping LS chips out for F chips for more speed to reach the 4mhz.. currently I have all mine as LS... which could be key to what speeds I can achieve.
When I upload your zip file to PCBWay for v1.6 it doesn't generate a preview but it does for v1.5. Would that indicate a problem with the gerbers ?
Hi, this is a *breadboard* version. There is no PCB design behind this schematic.
@@slu467 thanks !
Please make a video with Mandelbrot benchmark to compare overclocked mini ua-cam.com/video/bIj3xBmALxE/v-deo.html
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