Intel's Newest $350 Million Machine
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- Опубліковано 20 чер 2024
- In order to print the smallest structures in silicon, a massive ASML Twinscan machine is needed. Current generation technology can create line widths of 13nm, and those machines cost $150m. The new generation can go down to 8nm, and cost a massive $350m! In this video, we tour Intel's Oregon Fab where they've completed installing the world's first commercial High-NA EUV machine. It's in the calibration phase now, ready for testing.
[00:00] Twinscan NXE:5000
[01:20] NA and EUV
[03:00] Installation Logistics
[04:30] FIRING MAH LAZOR
[07:20] 10nm Line Widths
[09:20] 14A Roadmap... and Hyper-NA
[12:25] Touring The Fab
[14:15] Dr. Mark Phillips
[15:30] Tin Droplet Suppliers
[17:00] Visiting Other Fabs
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Welcome to the TechTechPotato (c) Dr. Ian Cutress
Ramblings about things related to Technology from an analyst for More Than Moore
#intel #highna #asml
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More Than Moore, as with other research and analyst firms, provides or has provided paid research, analysis, advising, or consulting to many high-tech companies in the industry, which may include advertising on TTP. The companies that fall under this banner include AMD, Applied Materials, Armari, Baidu, Facebook, IBM, Infineon, Intel, Lattice Semi, Linode, MediaTek, NordPass, ProteanTecs, Qualcomm, SiFive, Supermicro, Tenstorrent, TSMC. - Наука та технологія
When I applied for my graduation work (MSc, Eindhoven University of Technology), the assignment was to work on this machine. And this was still 1999... 25 years ago...
lol, and Intel tera herz 1000GHz leak was in 2001, 23 years ago.
I was working as a Master student on a EUV prototype "lamp" at the RWTH Aachen, Fraunhofer ILT and a spin-off company those days. Interesting times full of advancements, miss it. I also miss the beautiful old Aachen city and region with all the culture, clubbing, "beer-gardens", great food, and nature for mountain-biking around. Never got such a good work/life balance in any other region I worked ever after. I should have stayed.
It feels like Intel has been on 10nm for that long as well💀
i think you are colleague of my father, he works on ASML since ASM collaborate with phillips
In 1999 at best you could get a DUV machine. this is an EUV machine. Twinscans were introduced around the year 2000 so you might have experienced that one...
I am one of the software engineers that developed the software for it. I visited ASML EUV factory/cleanroom in Veldhoven a few months ago, there were EXE machines fully built and some other big modules being tested. It is amazing, you keep staring at it and each time you find something different about it. Making 10 nm features in high-volume is allien tech, it is almost half smaller than the current best high-volume process. In general, making features 50% smaller would reflect on 4x speed/performance or more logic, but because it is NA bigger only in one direction, the gain is limited to 2x. For Hyper-NA I think they are going for 4x gain.
185 wafers/h @$20k = $3,7 mil/h. it will return its $350 Mill cost in 4 days.
intel tera herz in Intel vault of future tech is collecting dust from 2001. while corporations are milking funny low sillicon gains for decades.
the problem of slow progress is EXACTLY because corporations don't want to throw away these machines. it pays for itself in like a week of production of chips and they keep using them for DECADES milking the market instead of actually doing some FAST progress.
not making any progress and using these machines for decades = printing trillions $$$ from sand. just have to slow the progress down to being as slow as possible.
@@rawdez_the gains are a few orders of magnitude lower then that. Keep in mind, there are thousands of process steps to make a wafer useful and millions of dollars a year are spent on keeping these overcomplicated machines running. Go work for a fab and you’ll figure out it’s not all sunshine and roses.
Many of my university friends work at Zeiss now building these EUV optics :)
And we put them to use 😋
The most precise optics ever created, way beyond the hubble lens.....damn right you're not humble about it 😄
It's mirrors, not lenses :) no more lenses possible at 13,5nm.. @paulmichaelfreedman8334
350mil is bloody cheap for a industrial machine this sophisticated.
Absolutely. It's literally holding the future in your hands. For ASML, their partners and their suppliers this is an incredible milestone, and this machine will pay Intel back for many years to come.
I would assume ASML also charges for handover and software to run the machine with or smth?
Else why only sell it for 350 mil?
Why is ASML worth 300+ billion whilst they only make maybe a dozen of these machines a year?
M or mi*
Def right cheap $350ml for such a complicated machine
New tech has made things cheaper but creates a pile of throw away rubbish
Make manufacturing back in your country
@@fatjohn1408 Company is usually quotting as having a worth related to its public/private stock market capitalization- which is very little to do with their actual assets on hand. Money generally only exchanges hands with investors to the company when stock is sold on the private market, or as IPO, or extra stock selloff
The things humans can make is kind of wild
check out Intel Tera herz - 1000GHz 2001 tech. these silicon producing machines should've been thrown into garbage a long time ago. for waaaay more mindblowing tech to replace it. but they make too much money for corporations so alas not going to happen soon.
Intel tera herz example shows that its even more wild what humans can make but just don't for some stupid reasons. like a lot of trillions dollars))
@@rawdez_ I see a lot of comments from you and they are all a bit crazy. You write like things are very simple and you know everything. Intel is NOT making Billions on an investment of Millions. Intel is barely profitable.
As for the terahertz transistor - that's ONE transistor, not a whole chip. A whole chip has billions of transistors... A terahertz CPU will, due to the speed of light, have information changing at one end of the chip while it's being processed at the other end. You can pipeline for this, somewhat, but pipelining is a very limited tool.
Also, what about stability and longevity?
The teraherts thing you know about is a fringe experiment... And you only hear about the one time it worked, not the hundreds of times it burnt the CPU, burnt the clock, etc...
@@rawdez_ whats a Intel Tera herz - 1000GHz tech?
@@-.369.- its 1000GHz transistors tech intel announced in 2001(apparently by mistake because nobody heard about it since 2001) that was ready for production and supposed to hit the market in 2005. and replace silicon. but didn't. because milking silicon instead is way more profits. btw "15nm" silicon tech also was announced as tested and working in 2001 but released (as 14nm) 13 years later.
You must have felt like a kid in the best candy store in the history of this planet.
He does have a taste for chips if the photos are anything to go by
Im just surpised its already installed. Intel got the machine in mid January and they are already this far. Serious business ^^
What is the point of gowning up if you leave your nose exposed and spraying nascal droplets everywhere?
I was happy that UA-cam recommended me this video. :) Like another commenter, I'm also a software engineer, but working farther away from the actual ASML machine, specifically developing a software platform for executing adjustment processes on the High NA EUV projection optics boxes. It's quite exciting to work on something that even just supports the manufacturing of these cutting edge machines. We had a tour at the Zeiss clean room, seeing both the older POBs and a new High NA EUV one, and this latter POB in itself is already gargantuan. It was an amazing experience. :)
Oh that's nice! I'd love a tour of Zeiss. (that rhymes!)
I'll see if my new ASML contact can get me in.
Ian is the champion of breaking down complex topics so even dorks like me can understand them.
ASML have shipped Twinscan EXE:5000, this is great news.
Thanks for keeping us in the (k)now
You missed some of the best bits, after vaporising the tin droplets you then need to stop the tin vapour from coating your $1M lenses...this was a very hard problem to solve!
I've heard stories, perhaps a topic for a future video!
@@TechTechPotatoWe probably will never know the names of the genius who figured it out.
@@mefobills279Probably a team effort
In my previous job, I help spec a desktop for one of these machines at a smaller scale. The machine was 2.5million and I was told go crazy with the cores. That one definitely is extremely HUGE
Now working for ASML. The equipment is very precise. Just the LASER for it is huge and has some serious IP in it's R&D.
that's so cool to catch a glimpse into a fab and actually see the latest asml euv fab machine.
11:10 I wish I could buy a 250nm machine from 1980s for home use.
Ngl I was thinking the same thing. Save up and build an experimental super low volume lab or something... Sadly, I'm sure even 1980s tech would be way out of any individual's price range.
Check out the work by Sam Zeloof. He built 1000 transistor chips in his Garage at the age of 18.
You will need about 15k in eBay parts but is possible
I bet with stamps using nano-imprint methods you could make a few tiny transistors. Connecting them together might be more difficult. 😮
I think the chemicals even 250nm machines use for their UV lasers would be difficult to manage.
Amazing. Best of luck to their facilities.
lol I am the guy that yelled at you guys for one of your hoods being inside out! 😂
The Sub-fabs are just like stacked chips which is pretty cool lol, great video Ian.
The math, chemistry, physics, engineering and technology in these things is off the chart crazy.
Excellent purchase from Entel. This machine is incredible and Intel's progress forced TSM and Samdung to also place orders with ASML so as not to be left behind.
I’m just a typical application development software engineer, I don’t have anything to do with this stuff, but i love learning about it
Thanks for pronouncing Oregon correctly!
What did it taste like? They let you take a bite right?
hell yeah, this was cool as heck and super informative, thank you for this quality content.
Incredible how this technology is enabled by the top expertise from all over the world. The sector is so vast and so complex that it is unthinkable that one single country could manage all different aspects of high-tech semiconductor technology.
Thank you Techtechpotato for producing this excellent video.
Greetings from the UK,
Anthony
Thank You For Your Presentation!
You are really great. while you describe your visits to foundries, it feels like being there...
im laughing, i thought it was the trailer for dune 3, nice video, thank you!
If you get any invites to more Fabs, (don't care how new or old) go on ALL of those Fab tours. Just keep traveling and visiting. This is where the rubber meets the road, semiconductor fabrication.
This video just blew my mind, earned my sub
It honestly both baffles me and restores my faith in humanity when I realize how much cooperation is needed to create and maintain something of this magnitude.
thanks for content
Worked on semiconductor equipment in fabs for 20 year. Loved it
Cool, great content!
Nice presentation!
I wonder what's the current line width in R&D? A nice plot would be cpk vs line width. or a results from a field exposure matrix.
Wow you have an amazing curiosity on all of these stuffs at such a young age. I was video gaming at your age without carrying about any of these hardware stuffs.
Dude I'm almost 40.
@@TechTechPotato in his context almost 40 is young. He's probably 70 or 80 now. /s
I'd love if you could bring us a tour of an OLED fab.
me too!
Gamers Nexus did some cool tours
Amazing! I couldn't understand a single word in this video but amazing ❤
Very well done. Most impressive :)
Awesome video
Always enjoy the fab visits and I'm really hoping you'll get a chance to hit up Intel's packaging facility in New Mexico.
that thumbnail caption, hahaha :D
It really is mind blowing just how small these parameters are.
If you shed an eyelash, you're spoiling an awful lot of stuff.
Amazing!
Great video 👍🏻👏🏻👏🏻👏🏻
Impressive archivement both ASML and Intel for trying to push the boarders of modern lithography even further.
Great video for the most advanced chip maker technology, also like to see the comments from all of you folks 👍🏻👍🏻
Not sure I follow your efficiency stuff @6:20 when you start with kWatts (power) and end with milliJoules/cm^2 (fluence). Units don't match and there is that 60 kHz pulse rate in there as well.
yes, the exact per pulse wafer dose is a commercially sensitive number. the input lasers aren't kWatt continuous, they are high repetition pulse - energy per pulse isn't said either.
Astonishing.
3:08 “Standard normal sized people” had me 💀
I know this is off topic, but any indication that Tenstorrent is going to go public?
It won’t be until 2026 at the earliest. Tenstorrent will remain private with the help of Samsung just like OpenAI will remain private with the help of Microsoft.
Out of curiosity, how does the licensing work for those pictures taken by CBS? Like are they just released into the public domain or did each journalist/org on the tour get some kind of license? What kind?
He said that everyone in the tour is required to share their media with everyone else including Intel
@@BGraves Yes, I'm asking how sharing translates into licensing. I suspect they offered some kind of license to publish to those entities as well but is it unlimited, can they sublicense or did they just release it into the public domain?
i used to work in f11, f12 and f22. i worked with D2 people in oregon. crazy that they're a month behinds asml. very smart of them to get their engineer's feet wet as clearly they got out of shape re: euv in general. decisions like that tended to bear fruit. we would literally do the same thing downstream for the high vol mfg sites training from the d2 folks as they did development.
I love how in all these ASML videos there’s always someone who says they worked on something.
we're everywhere!!
True, trey either are very proud of being involved or they are lying and wish they were actually involved.
Some 25ish years ago I got to tour a DuPont fab
you gave a informative discription of wafer fabbing
Can’t imagine the PMs on this thing
Would be amusing if the tin droplet feed worked like a shot tower.
Great video thanks for sharing and caring but was he resonance mode 0:31?!
Imagine the truck driver looking at his cargo sheet and seeing the cargo value when transporting these machines 😳
Its a miracle that something doesn't break at least once a day on that machine!
love it when a tech has a chair ,
The fact that the first thing that came to mind from that blurred background was High NA says something ig
It will more than pay for itself
in 4 days. with 185 wafers/h @$20k/wafer price $350 mil machine pays for itself in 4 days. literally.
And they made, shipped, installed and run everything with solar panels. It's amazing they can do all this with net zero.
What is the connection between ASML 8nm lines and the process for CPUs declared by Intel/tsm?
Current metal pitch (from imec) in N5 is 28nm, using 6 metal tracks for FinFET. N2 is expected to be 21nm with 6 tracks, while A10 in 2028 is expected to be 16nm with 5 tracks. Though this is the densest IO transistors, not the leading edge super fast transistors.
@@TechTechPotatoIt’s amazing that ASML can achieve 16nm metal pitch in A10. How will the A10 process mitigate electromigration?
@@tringuyen7519 agreed I think this would be an issue, how do they fix?
Think i read : Intel just adds a text these chips will fail after 50.000 hours i think. That like 3.4ish years of run time.
A good size comparison would be to a train locomotive. Basically, those things are trains, just they make microchips instead of hauling goods and people.
What happens to the vaporised tin droplets? I would assume they would cause a build-up of matter on surrounding surfaces.
I believe they do, to a certain extent.
amazing!
Amazing beast.
world class content
I worked in that building, in the basement. That's where the pumps are located.
The money numbers are definitely headed in the direction of pentagon sized money numbers
my god these tools are extreme
Question - what about vibration isolation? Was this machine built on its own support? Was hydraulic suspension or dampers used? Did they have to re route aby truck traffic?
Are the machine getting more vibration insensitive or vibration sensitive ??
Worked in this industry for over a decade. Safe to say that vibration is a big no no.. So almost all these machines sit on their own isolation platforms with actively controlled levelling and stabilisation systems.
@@AmrishKelkar Thanks.
Just the leveling and vibration isolation could be an interesting video. with smaller features, it seems external truck and internal parts moving Vibrations becomes a larger issue.
the entire fab is seismically isolated, as is every floor in the fab, as are the tools themselves. To tell you how sensitive the tools in the fab are to vibration, we often know in the fab about earthquakes before we hear it on the news. Quakes in Alaska and Japan will cause some lithography tools to error out.
So yeah, the buildings are incredibly vibration protected and it still often isn't enough.
@@CRneu "Quakes in Alaska and Japan " cause errors. Wow.
Nothing like a real world report
I do not understand how people can make so many fascinating things.
the burka was so ahead of its time
This EUV chip manufacturing technology is probably the peak of cumalitive human technology? If there printing 10nm lines how come people are releasing 3nm and 5nm & 7nm in marketing theory, chip structures? is that in a different orthoganol direction … ie vertical to the wafer layer itself?
When you hear people talking about process nodes like 7nm, 5nm, 3nm, that's not an actual measurement, it's just a name. Ever since we went 3D, those node names aren't actually related to anything built on silicon.
@@TechTechPotato - you should have mentioned that in the video.
I thought straight away - what about 3nm chips?
I did? I mentioned node names are just names, not actual dimensions. I've said it in dozens of videos.
@@TechTechPotato - OK - I missed that.
You are speaking to lay people not semiconductor experts.
Flown to Seattle? I'd love to know why they couldn't fly it into PDX and just drive it the 10 miles to the fab from the airport. Seems kinda weird.
Or just fly into Hillsboro across the street from the fab
I have landed many times at Hillsboro. No 747 can land there. We move the scanner in a 747
@@arrdubuHillsboro runway is 6600ft. SEATAC is 8500-11900ft. A fully loaded 747 requires about 10000ft of runway. Not possible.
PDX might not have the support infrastructure to unload. SEA is a much larger airport with more capabilities.
@@CyrusTabery I've watched many 747s and other large aircraft land at Hillsboro.
I drive by this on my way to work every day but I never knew what was inside
so at what point does it stop being ultraviolet and start being xrays?
EUV was actually called 'soft xray' back in the 80s. The designation is largely arbitrary.
According to a NASA xray science page i found, xrays are 0.03 - 3nm.
3:28 You bred raptors?
Mostly ancient Minoan to me, but if it results in powerful graphics that can run on AAA batteries then money well spent.
it's ok we can wait
I don't want to imagine how complex these machines are
What was the old $350 Million machine?
Numbers are bit inaccurate on the laser itself - there is 4 Resonators that step up the 2 smaller lasers ( baby lasers!) bringing a low power then an additional smaller amplifier to around ~150 watts all the way to an Average output power of ~30kW. The Pulse for the flattening is lower powered - but the Pulse that creates the EUV can be around 20MW per pulse! (think, we are averaging across 50 khz) but still - incredibly powerful - one of the resonators can cut through 2 inches of steel with ease - and CYMER/ASML/TRUMPF said... lets put 4 of them together! Look up TRUMPF EUV for a better understanding of the laser itself!
Of course Dr. Ian has big chip energy. You can see it in broad day light.
Broad EUV light :)
@@TechTechPotato That's what I meant :P
I wouldn't be surprised if the vast majority of exposures on modern CPUs are still done with DUV
They still are. A modern 17 layer chip uses EUV for only the first 2-4 or perhaps 6.
you don't immediately use new wavelengths to create your latest chips. New nodes are only used in specific layers, and there can be dozens of layers in a single chip. So today's cutting edge chips are only using EUV for maybe 2-3 layers. The rest are "old" nodes.
I guess I won't be building one of these out in my workshop.
I thought the background on 0:52 was a bandaid on a thumb 💀
It sounds like light magic
You might need to interview Groq
I have some questions that I hope someone can answer for me.
1. Why does it require two passes with regular EUV? Is it because the light source is more diluted and can't do the job in one go? Or more like its a bit blurry?
2. From my memory of chemistry at university, 8nm should equate to about 40 pr 50 atoms. How on earth do you prevent or control all kinds of weirdness that result from electron tunneling?
3. Are we basically at the fundamental limit of how small we can go? If so is it just how well the architecture can be improved, and how much can AI improve it, or will it become a case of stacking layers on top of layers, potentially with microstructures that allow more efficient cooling?
For your number one, it might be because of multi-pattering. In short, you can create structure smaller than your wavelength if you multi-pattern onto the silicon. Basically you're multi-exposing your photo resist to create structures you can't make with a single reticle/mask at that wavelength.
It's rumored that pattering is how china is somehow managing to keep up with EUV despite not having current euv tools.
That might not be what Ian was talking about though.
@@CRneu but how? It doesn't make sense.
@@Alex.The.Lionnnnn The best that I can put it is this: Using phase shift masks we are taking advantage of interference in order to etch features that are much smaller than the wavelength allowing for example the etching trench line that is just 8 nanometers wide (your line width) in the silicon. Remember in a positive photoresist such as used in EUV, its the exposed parts that get etched away. The problem is due to the Raleigh criterion you cannot etch your 8 nm wide line closer than 50 nm (your pitch) from each other if you have low-NA (0.33) EUV. Now if you etch your first set of lines, coat it again with photoresist expose another pattern this time offset just enough so that it etches right in the middle between the lines that you previously etched. You now have pitch of 25 nm. You can now pack twice the number of lines in the same space. Repeat the process you now have a pitch of 12.5 nm. In practical terms where you where previously limited to a finFET with a 50 nm wide fins, by using 3 patterns you now have 12.5 nm fins. If you have a higher NA you can have a finer pitch with having to resort to as many patterns and exposures.
@noob360 ahhhh ok I'm with you. Cheers.
can we assume that Arrow Lake is using this new machine ?
Its amazing to me that a machine that big is needed to make a small chip
If you fractor in the sells of chips, this is ACTUALLY one of the most advanced and expensive piece of equipment
is this the EXE:5000 or the EXE:5200? should be the 5000 right?
5000 indeed.
6 lasers coming together... Sounds like the Death Star...
Would be interesting to see if the machine comes with an IKEA style assembly booklet.
Funnily enough, I did ask if it did