VHDL ENTITY| How To Write a VHDL Entity

[@nehanavale1967]

Grate explanation mam...plz take more video on vhdl ...on modeling styles an other part of vhdl

[@EasyElectronics975]

Yes they will be uploaded one by one

[@finnyphilipbiju4520]

Thanks for this new video series.
Can you also share some links to resources. I want to learn array operations using vhdl and writing a testbench for the same. I am unable to find any resources in the internet for getting it done. Can u please help
Basically I want to do declaration of 2 arrays, find the maximum value in it and store that value in a register.
To be done in xilinx vivado

[@taraksriram63]

thanks for the vhdl series mam.........great help

[@EasyElectronics975]

Please support our channel , share among friends

[@Ravikumar-ir8kg]

Great explanation mam ... 🥰🥰🥰

[@ananyaraje921]

Do more explanation on modelling of vhdl and differences btwn them

[@EasyElectronics975]

Yes today I have posted a video

[@sunithavar7017]

Mam why we should not use semicolon after entity and2 is first line mam

[@honeythatipamula8534]

Mam..how to see our article is approved or not?...nd if approved wr we can see that?..in articles insider website..

[@EasyElectronics975]

You will get a mail on the same, within 1 week

[@honeythatipamula8534]

@@EasyElectronics975 But it Said 48 ,72 hours it will get.

[@nithinxjohnson2983]

I have one doubt why no semicolon provided after c: OUT BIT inside the bracket just like done for a,b: IN BIT.

[@EasyElectronics975]

For the last variable the semicolon is placed after the bracket. It's the syntax of VHDL

[@nithinxjohnson2983]

@@EasyElectronics975 Ok thank you so much. Keep doing more VHDL videos.

[@EasyElectronics975]

@@nithinxjohnson2983 sure

[@rajivgandhi3252]

Thank you mam

[@manikandanthirupathi6727]

Chechi post more videos on VHDL please........

[@EasyElectronics975]

Yes after 100 K we will start VHDL back to full fledge

[@saivamshi5853]

if an interviewer asks us, what is the major difference between verilog and VHDL? how to answer it ma'am

[@EasyElectronics975]

I am sharing a link please go through it
pediaa.com/what-is-the-difference-between-verilog-and-vhdl/

[@vigneshv1378]

Mam what is exact buffer (from one source) ?

[@EasyElectronics975]

It's like inout itself.

[@vigneshv1378]

@@EasyElectronics975 thanks for ur reply mam

[@ananyaraje921]

Make more videos on vhdl coding

[@EasyElectronics975]

Coming from august

[@Grace-uv6uu]

mam any jobs related to vhdl for freshers ??

[@EasyElectronics975]

Many jobs are there please see intel , dell , qualcomm these companies for updates