Easier UVM - Register Layer

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  • Опубліковано 19 січ 2025

КОМЕНТАРІ • 11

  • @rathnashree723
    @rathnashree723 Рік тому +1

    Thank you for this video because I got to know inner level engineering of register layer. The explanation was fantastic. Once again thanks

    • @DoulosTraining
      @DoulosTraining  Рік тому

      You're so welcome - glad you found it useful, and thanks for taking the time to get in touch with us to let us know!
      Keep an eye on www.doulos.com/knowhow for more UVM based content, or head over to the training links if you need to build comprehensive understanding :)

  • @benjamingittins2174
    @benjamingittins2174 Рік тому

    Today, open source UVM register model generators are available: (1) PeakRDL using SystemRDL 2.0. (2) the Open-Register-Design-Tool (ORDT) using SystemRDL 1.0. SystemRDL is a powerful way to describe register models in a human readable way. Those models can then be used by generators to create documentation, UVM register layer models, C++ hardware abstraction layers, and so on.

  • @syedtaahir
    @syedtaahir 8 років тому +2

    Thank you so much John!!!! was waiting for long time!!! please upload videos for scoreboard, monitors, coverage

  • @uvm1.2
    @uvm1.2 Рік тому

    Hi John, reg2bjs doesn't work for me, can you tell me what could be the cause of the problem in general? Thanks

  • @manojrr87
    @manojrr87 2 роки тому

    When you say choice of physical interface, are you referring to the communication protocol?

  • @aiwashiwanov4463
    @aiwashiwanov4463 5 років тому

    Helped. Thx.That's very complicated at all, but most things understandable.

  • @saneel1988
    @saneel1988 Рік тому

    Awesome explanation!!

  • @bobo_for_all
    @bobo_for_all 3 роки тому

    So, much informative. Thankyou..!!

  • @sonap9206
    @sonap9206 6 років тому +1

    useful and neat video

  • @anjaneyuluc8814
    @anjaneyuluc8814 5 років тому

    Thank you john