Critical path delay is the worst case delay right? So why don't we take the case where every single adder in all stages are in generate mode, in that way the cout can't bypass and has to go through the entire ripple chain and will create much more delay than the case shown above where only the first bit of first stage id GEN.
6:22 Why we are taking first FA to be in generate mode.? is it because Taking G=1 means we have make P=0 , which will eventually select the critical path going through each FA? Taking P=1 in each FA , will directly propagate the Carry through Multiplexer , which will make it independent of N? Right?? If it is so!! Then that means we can Take G= 1 for any intermediate FA.( right?)
if G=1 is taken for any intermediate block then all the blocks before it won't be contributing for the delay and delay will be calcuated for all the blocks after that intermediate block. So that won't be the worst case delay.
Because that 4 bit segment having generate will start computing the Co. Only when it is just the very first bit A0 is in generate mode, that every segment has to wait for the output of the previous segment.
operation is complete only after the last sum is generated..so at the last adder we need to calc the time to gen (m-1)th carry as it will be used to evaluate the mth sum...this total time is given by (m-1)tcarry+tsum
@@Engineer884 Hello, m*tcarry is the time required to generate cout of FIRST STAGE. And (m-1)*tcarry+tsum is the time taken by carry to propogate from 1st full adder to last full adder of LAST STAGE + time required to generate last bit of the sum output after the arrival of carry to last full adder (since sum generates after arrival of carry)
Critical path delay is the worst case delay right? So why don't we take the case where every single adder in all stages are in generate mode, in that way the cout can't bypass and has to go through the entire ripple chain and will create much more delay than the case shown above where only the first bit of first stage id GEN.
6:22
Why we are taking first FA to be in generate mode.?
is it because Taking G=1 means we have make P=0 , which will eventually select the critical path going through each FA?
Taking P=1 in each FA , will directly propagate the Carry through Multiplexer , which will make it independent of N?
Right??
If it is so!! Then that means we can Take G= 1 for any intermediate FA.( right?)
Yes, you are correct. The point is to make the circuit use the longer path. So technically, any one of the full adder blocks can be in Generate mode.
if G=1 is taken for any intermediate block then all the blocks before it won't be contributing for the delay and delay will be calcuated for all the blocks after that intermediate block. So that won't be the worst case delay.
Understood the lecture.
But its quite lenghty to note that much information in notes 😂😂😅
you can copy the yt transcripts in a word file and highlight the important parts...
Why we aren't taking kill in any situation?
It's not in a situation involving critical path delay. Kill will always decrease the delay below the critical delay.
why tgp should be included ? carry for first 4 bit adder and tgp will be computed simultaneously.
You cannot calculate carry without G and P.
why is not the worst case a condition when first bit of each stage is in generate mode ??
Because that 4 bit segment having generate will start computing the Co. Only when it is just the very first bit A0 is in generate mode, that every segment has to wait for the output of the previous segment.
Why (M-1)tcarry and not M*tcarry for last segment of the adder??
operation is complete only after the last sum is generated..so at the last adder we need to calc the time to gen (m-1)th carry as it will be used to evaluate the mth sum...this total time is given by (m-1)tcarry+tsum
@@subhrasen1395 when m*tcarry is included, then why to include (m-1)*tcarry again. By including mtcarry we are automatically incorporating (m-1)tcarry
@@Engineer884 Hello,
m*tcarry is the time required to generate cout of FIRST STAGE.
And (m-1)*tcarry+tsum is the time taken by carry to propogate from 1st full adder to last full adder of LAST STAGE + time required to generate last bit of the sum output after the arrival of carry to last full adder (since sum generates after arrival of carry)
sir where will I find the slides? Thank You
Iitm website