Digtal Logic Design crash course in 4 hrs [Urdu/Hindi]

#digitaldesign #logicdesign #verilog
This video covers complete Digital Logic Design course. Intended audience is lazy students who want to cover everything last night before exam, people who want to revise stuff for qualifiers or interviews in short time and self paced learners who do not have time to watch complete 16 weeks course.
First 2.5 hrs cover most of the content generally taught in Digital Logic Design courses. Next 2 hrs cover Verilog and various design examples that might be useful for advanced audience.
Slides can be downloaded at
tinyurl.com/dld-slides
Jump to relevant sections by clicking time tag below:
(0:00) Number Systems (conversions, 2's complement form)
(28:06) Boolean Algebra and logic gates (SOP, POS, Demorgan's law)
(53:30) Gate level minimizations (Kmaps)
(1:27:07) Combinational Circuits (Decoder, Encoder, Priority Encoder, Mux, Demux, Comparator, Adder/Subtractor, Multiplier)
(1:54:40) Sequential circuit design (Latches, Flipflops, State machines)
(2:28:48) Sequential circuit analysis
(2:39:07) Verilog for synthesis
(3:25:21) Verilog for simulation
(3:53:28) Design examples review (level to pulse, digital clock, BRAMs, VGA)
(4:02:46) Processor design example

[@RenzymEducation]

There is a mistake at 2:23:47
Z should have been equal to Y + Q (instead of YQ). The resultant standard POS form will be (Q + X + Y)(Q + X' + Y) i.e. it will be 0 for maxterms M0 and M2 and 1 otherwise in truth table

[@ZeeshanKhan-tg1gi]

Good course .I will be with you.

[@vishalmoladiya2735]

True inspirational and hardworking person! God bless you! Love from India

[@RenzymEducation]

Thanks Vishal

[@AbdulHaseeb091]

Thanku so much sir God bless you❤hmsha.khush rhyn kash ap jaisy teacher hummy har subjects.k mil jty❤

[@RenzymEducation]

Thanks. Net pe mil jaen ge

[@muhammadammar6413]

Thankyou so much sir ❤️ revised whole course in few hours. Thanks 👍

[@RenzymEducation]

Most welcome

[@astrosohaib]

sir i love you bohat helpful thi video

[@RenzymEducation]

It's my pleasure

[@haroonabdullah7516]

one question ask from you please guide me i check this lecture one thing is not understand yet when he was applying gates of three boolean expression the diagram of second one the position of variable a b c change why?? VEDIO PART 2 32 GATES

[@ahsanalirafaq805]

Sir please make a lecture series on digital signal processing with implementation on FPGA or ARM cortex. Really need that subject.

[@RenzymEducation]

Thinking about it, but unable to find time

[@mohitnegi4307]

Sir, what software do you use for video making

[@RenzymEducation]

This video was recorded using zoom. At times I use OBS studio too. For editing, I use shotcut.

[@MrShadow65]

sir can we have the slides
which is shown in this video

[@RenzymEducation]

I have added link to slides in video description as well. Here is the link
tinyurl.com/dld-slides

[@izharqazi5836]

Sir ye slides share karsaktey hai?

[@RenzymEducation]

I have added link to slides in video description as well. Here is the link
tinyurl.com/dld-slides

[@sarahal5627]

I wish there was an English subtitle

[@RenzymEducation]

For the second half of video there is a video in English
ua-cam.com/video/nblGw37Fv8A/v-deo.html

[@sarahal5627]

@@RenzymEducation Thank you so much!!

[@nedasamad8484]

7

[@mr.s7397]

Sir please share the notes

[@RenzymEducation]

I have added link to slides in video description as well. Here is the link
tinyurl.com/dld-slides

[@yoolpool415]

Isn’t 46:52 wrong?

[@RenzymEducation]

I think its correct. Can you exactly point out what you find wrong? I suggested a shortcut that this time tag that does the same thing as repeated application of the formula

[@sportshub949]

Who else from vu?

[@abdurraafey6404]

Yesss! Virtual Universityyy..

[@AbdulRehman-xo6kq]

@@abdurraafey6404 vu ky to aisa lecture ni h

[@AbdulRehman-xo6kq]

Ap vu sy h

[@sportshub949]

@@AbdulRehman-xo6kq yes