CO30 - Multi-bus Organization of Processor

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  • Опубліковано 25 гру 2024

КОМЕНТАРІ • 9

  • @krrsah2004
    @krrsah2004 Місяць тому +1

    nice teaching, so simple explanation ,thank you ma'am 🙏

  • @john6461
    @john6461 2 роки тому +3

    Superb teaching 👌🏻

  • @societystalker47yearsago65
    @societystalker47yearsago65 2 роки тому +3

    Thank you ma'am

  • @Bhavanisaleela
    @Bhavanisaleela Місяць тому +3

    Explanation Telugu lo cheste bagunnu mam

  • @walkthroughonthego2476
    @walkthroughonthego2476 Рік тому +2

    is iiim possible?

  • @thinkunique5817
    @thinkunique5817 4 роки тому +8

    Mam your explanation is too good but for the better understanding you could have written the sequence of the control signals (like 4 instruction list)
    so that it Could have been understood more effectively.
    also you are saying wrong mam what you are given example instruction and what you are explaining is mismatching.. because you wrote Add R4,R5,R6
    when this instruction you are considered in this case R6 will be the output but you are saying R4 as the output.
    Correct it mam

    • @ezcse
      @ezcse  3 роки тому +3

      It depends upon the design of the ISA (Instruction Set Architecture). Here I am assuming that the first operand (R4) is the destination register and the second and third operands (R5, R6) are the source registers. If the ISA you are using has the first and second operands as source and third operand as destination, then R6 will contain the output.

  • @fatehgarhiya
    @fatehgarhiya 8 місяців тому +2

    are yrr hindi mei bhi bnalo agr english me smj ata hota toh apke paas kyu aate😂