Multiplexer implementation using Pass transistor and Transmission Gate logic

[@theoryandapplication7197]

thank you very much sir , the video that i am looking for

[@harshmagnani4501]

Please upload full playlist.. this is module 3.2, where are module 1, 2...?

[@AaryanUpadhyayaWho]

Couldn't just 6 TGs be used for 4:1 MUX - (2 + 2) TGs for selecting I₀/I₁ and I₂/I₃ based on S₀ and 2 TGs to select one of the outputs from the previous selection based on S₁

[@InderjitSingh87]

Yes, it can be done.

[@Mishu2047]

Hello sir

[@Mishu2047]

I like your video tutorials . Can you please send me the link of combination mos logic circuits chapter 7 of cmos digital Integrated circuits by Kang. I am unable to find the VIL,VIH of cmos NOR2 gate. Please help me for which I shall be grateful to you.