This was an incredible short and helpful starter series so I can use my basys3, thank you. Only problem I had was with the hardware manager since the first TWO micro-usb cables that I tried were power-only. WTF!
thank you so much, i was trying to figure out why my switches wouldn't do anything and this video helped me realize that my xdc file was configured wrong after looking at the IO ports
Thank youso much for the tutos, they really helped me out! Just one question: At 5:17, for the schematic view, I don't have the the "package" tab (and I can't find it). I solved it by creating the constraint myself and copying what you have in yours, but I think it's not always the best way. Any idea of what happens? I'm working with VIVADO 2016.4 and the rest is almost the same as yours . Thanks a lot !
Good tutorial. I noticed that I get a syntax error using timescale, so I omitted it. Looks like #100 defaults to 100ns without the timescale line in code.
I am currently following your tutorial on design with vivado using FPGA. I am using Zedboard FPGA to demonstrate what you have shown to us. But Hardware manager cannot detect my Zedboard FPGA. What could have happened? I need your help pls?
have you resolved the issue with the hardware manager? I am also having the same issue but with the basys 3 board and I am using the Vivado version 2022.1
Digilent should kiss your hands for creating these videos. Very clear and very useful.
This was an incredible short and helpful starter series so I can use my basys3, thank you.
Only problem I had was with the hardware manager since the first TWO micro-usb cables that I tried were power-only. WTF!
this is the best tutorial on youtube thanks a lot
thank you so much, i was trying to figure out why my switches wouldn't do anything and this video helped me realize that my xdc file was configured wrong after looking at the IO ports
Thank youso much for the tutos, they really helped me out!
Just one question:
At 5:17, for the schematic view, I don't have the the "package" tab (and I can't find it). I solved it by creating the constraint myself and copying what you have in yours, but I think it's not always the best way. Any idea of what happens? I'm working with VIVADO 2016.4 and the rest is almost the same as yours .
Thanks a lot !
The package view is available after you do the Synthesis. You can then click on Open Synthesized Design.
On the upper right-hand side of the program you'll see a drop-down window saying default layout there you can see the IO Planning
@@luisperez3507 Thank you!
@@luisperez3507 I love u
Good tutorial. I noticed that I get a syntax error using timescale, so I omitted it. Looks like #100 defaults to 100ns without the timescale line in code.
I am currently following your tutorial on design with vivado using FPGA. I am using Zedboard FPGA to demonstrate what you have shown to us. But Hardware manager cannot detect my Zedboard FPGA. What could have happened? I need your help pls?
have you resolved the issue with the hardware manager?
I am also having the same issue but with the basys 3 board and I am using the Vivado version 2022.1
thankyou so much for the video :)
thank you so much bro