This is great!!! make more videos, you are a natural youtuber. I'm just starting to learn verilog and wondering if it isn't better to just start with system verilog or if I should learn verilog first and then add sv. The learning curve has been very steep so far. A video on how to get basic tb up and running with verilator and gtkwave would help newbies I think and compliment you rother verilator video.
Thanks for the feedback! I will hope to have an intro SystemVerilog tutorial by April 1st. :) You should start with SystemVerilog because the features `logic`, `always_ff`, and `always_comb` are better than their Verilog counterparts. Although, all Verilog syntax is included in SystemVerilog, so you don't have to use any other purely-SystemVerilog features. When you're ready, I recommend learning enums, structs, multi-dimensional packed arrays, and unbasedunsized literals. I do have this basic explanation of SystemVerilog syntax if it would be valuable: github.com/sifferman/labs-with-cva6/blob/main/guides/synthesis.md
@@BitByte2Thanks for the advice. A video I'd really really like to see is how to connect a MCU like an ESP32 and how to design a protocol to bridge to some of it's peripherals like ADC/RMT/I2S. I've been playing with something called linuxcnc-rio that has a ton of potential and I'd like to integrate MCU's to expand it's capabilities particularly for slower stuff more suited for an MCU. I've always worked at way higher abstractions like json/msgpack/http/udp/tcp so it has been a big struggle for me to take what I want to do down to HDL.
Thanks for the great tutorial ❤
Glad it was helpful!
This is great!!! make more videos, you are a natural youtuber. I'm just starting to learn verilog and wondering if it isn't better to just start with system verilog or if I should learn verilog first and then add sv. The learning curve has been very steep so far. A video on how to get basic tb up and running with verilator and gtkwave would help newbies I think and compliment you rother verilator video.
Thanks for the feedback! I will hope to have an intro SystemVerilog tutorial by April 1st. :)
You should start with SystemVerilog because the features `logic`, `always_ff`, and `always_comb` are better than their Verilog counterparts. Although, all Verilog syntax is included in SystemVerilog, so you don't have to use any other purely-SystemVerilog features. When you're ready, I recommend learning enums, structs, multi-dimensional packed arrays, and unbasedunsized literals.
I do have this basic explanation of SystemVerilog syntax if it would be valuable: github.com/sifferman/labs-with-cva6/blob/main/guides/synthesis.md
@@BitByte2Thanks for the advice. A video I'd really really like to see is how to connect a MCU like an ESP32 and how to design a protocol to bridge to some of it's peripherals like ADC/RMT/I2S. I've been playing with something called linuxcnc-rio that has a ton of potential and I'd like to integrate MCU's to expand it's capabilities particularly for slower stuff more suited for an MCU. I've always worked at way higher abstractions like json/msgpack/http/udp/tcp so it has been a big struggle for me to take what I want to do down to HDL.