Since a similar circuit is used in the frontend of many pieces of high-impedance input test instruments, a blocking cap is generally always shown (for the safety of a novice copying the circuit). Since one cannot trust a user after the sale, or after construction, it's best to place two 600V coupling caps in series, say two 22 nF for the cap in question, because the instrument may be used to test old tube equipment.
Let me add that even though most educational institutions only teach solid-state theory these days, a quick premise on vacuum tubes would help the student, because when they understand how they work, solid-state is very similar, especially FETs.
@@craxd1 Sure, but time is a limited quantity in any college/university program. If the students and I had unlimited time, I'm sure the curriculum would be different. As it is, there is the constant question of what "old tech" has to get thrown out in order to make room for the latest and greatest. This is complicated by the fact that legacy equipment is still out there, but at what point do you say, "No, this other bit is more important now"? It can be a quandary, but then again, engineering is all about achieving balance.
The circuit in the video *does* include an input blocking cap (extreme left). It is not needed for this bias if there is no DC offset from the signal source, but would be placed there for protection from external DC.
rL is the AC load impedance (sorry for the shorthand, rL is r-subscript-L). RD is the DC drain resistance and is part of the AC load (hence, RL in parallel with RD, or rL; recalling that we always use lower case r for AC and upper case R for DC). Just look at it this way: You want to determine the AC impedance that the FET is driving. What's hanging off of the drain? That's the drain resistor in parallel with whatever load this is connected to (i.e., far side of coupling capacitor).
this video is life saver, thanks but i need to ask, i need to design an amplifier circuit which has 30 gain. But it doesnt work for the values above 100 mV. Is it normal?
The circuit uses self bias. You can either use a self bias graph or the rather long equation that produced that graph. You will find both in the JFET Bias chapter of my free Semiconductor Devices text (follow the link to my website).
Why is gm0 = -2 Idss / vgs off ? Why are we multiplying Idss by -2 ? And why are we using vgs off to determine the max gm0 ? Isn't vgs off when no current is flowing?
The gm0 equation is derived from the general transconductance equation by taking the derivative. These questions are answered in detail in chapter 10 of my free OER text, Semiconductor Devices: Theory and Application (section 10.2, JFET Internals). Follow the links in the video description and download your copy in PDF or ODT format (or, you can read it on-line via Libre Texts). Your choice.
The circuit uses self bias. Check out the video on that for details, but in short, the drain current established a voltage across the source resistance which means that Vs is positive. Meanwhile, there is no bias on the gate, so its DC potential is approximately 0. Thus, Vgs is negative.
@@ElectronicswithProfessorFiore imma fool, this is self biasing ckt alrd. Thanks. Btw sir can you make video on voltage divider biasing.. I not sure how it works bcaz the gate voltage is more than the source(if source is grounded)..
@@diago2805 That's what I call a combo bias. Typically it's done with a negative source bias supply. The voltage divider version just shifts everything positive to avoid the second supply. It's covered in my semiconductor devices text (free download, see the video description for links).
EXCELLENT LECTURE!
Since a similar circuit is used in the frontend of many pieces of high-impedance input test instruments, a blocking cap is generally always shown (for the safety of a novice copying the circuit). Since one cannot trust a user after the sale, or after construction, it's best to place two 600V coupling caps in series, say two 22 nF for the cap in question, because the instrument may be used to test old tube equipment.
Let me add that even though most educational institutions only teach solid-state theory these days, a quick premise on vacuum tubes would help the student, because when they understand how they work, solid-state is very similar, especially FETs.
@@craxd1 Sure, but time is a limited quantity in any college/university program. If the students and I had unlimited time, I'm sure the curriculum would be different. As it is, there is the constant question of what "old tech" has to get thrown out in order to make room for the latest and greatest. This is complicated by the fact that legacy equipment is still out there, but at what point do you say, "No, this other bit is more important now"? It can be a quandary, but then again, engineering is all about achieving balance.
The circuit in the video *does* include an input blocking cap (extreme left). It is not needed for this bias if there is no DC offset from the signal source, but would be placed there for protection from external DC.
When calculating the Vout (at 05:30) Why we multiply with rL but not RD?
Thx for the video!
rL is the AC load impedance (sorry for the shorthand, rL is r-subscript-L). RD is the DC drain resistance and is part of the AC load (hence, RL in parallel with RD, or rL; recalling that we always use lower case r for AC and upper case R for DC). Just look at it this way: You want to determine the AC impedance that the FET is driving. What's hanging off of the drain? That's the drain resistor in parallel with whatever load this is connected to (i.e., far side of coupling capacitor).
this video is life saver, thanks but i need to ask, i need to design an amplifier circuit which has 30 gain. But it doesnt work for the values above 100 mV. Is it normal?
Thanks a lot for the video. how did you get the 0.38 of Idss (from gm0.Rs being 2)?
The circuit uses self bias. You can either use a self bias graph or the rather long equation that produced that graph. You will find both in the JFET Bias chapter of my free Semiconductor Devices text (follow the link to my website).
Why is gm0 = -2 Idss / vgs off ?
Why are we multiplying Idss by -2 ?
And why are we using vgs off to determine the max gm0 ?
Isn't vgs off when no current is flowing?
The gm0 equation is derived from the general transconductance equation by taking the derivative.
These questions are answered in detail in chapter 10 of my free OER text, Semiconductor Devices: Theory and Application (section 10.2, JFET Internals). Follow the links in the video description and download your copy in PDF or ODT format (or, you can read it on-line via Libre Texts). Your choice.
IT INVOLES USING THE CALCULUS BY TAKING THE DERIVATIVE THIS EQUATION AND,DOING ALGEBRIAC SUBSTUTION.
Sir how the gate-source is in reverse bias?
The circuit uses self bias. Check out the video on that for details, but in short, the drain current established a voltage across the source resistance which means that Vs is positive. Meanwhile, there is no bias on the gate, so its DC potential is approximately 0. Thus, Vgs is negative.
@@ElectronicswithProfessorFiore imma fool, this is self biasing ckt alrd. Thanks.
Btw sir can you make video on voltage divider biasing.. I not sure how it works bcaz the gate voltage is more than the source(if source is grounded)..
@@diago2805 That's what I call a combo bias. Typically it's done with a negative source bias supply. The voltage divider version just shifts everything positive to avoid the second supply. It's covered in my semiconductor devices text (free download, see the video description for links).
Thanks