Arm's Weakly-Ordered Memory Model and Barrier Requirements - Ash Wilding, Amazon

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  • Опубліковано 25 гру 2024

КОМЕНТАРІ • 7

  • @YouveBeenCabadged
    @YouveBeenCabadged 2 роки тому +1

    Thanks! I read the barrier litmus test earlier today, and it was completely indecipherable without this video.

  • @klaboosterbaer3720
    @klaboosterbaer3720 2 роки тому

    Thank you so much for sharing this. I think you cannot explain it better!

  • @dneary
    @dneary 4 місяці тому

    Thank you for this very clear explanation of DMB, DSB, and ISB. My question, surely very dumb, is (1) what tools can I use to identify when a piece of software (say, the JVM or Go runtime) are over-zealously using barriers (either overscoped, or unnecessary barriers), using userspace tools? And what does it look like in high-level code (C/C++, Java, Go, Rust, C#) to optimize this (either reducing scope, moving from a DSB to a DMB, or removing unnecessary barriers)?

  • @xwtek3505
    @xwtek3505 6 місяців тому

    In 48:18, why is it DSB OSHST and not DSB SYST?

  • @amosmim
    @amosmim Рік тому

    any chance that the slides are shared somewhere? :)

  • @xihan6950
    @xihan6950 3 роки тому

    At approx. 21:45, it is assumed that the DMA buffer is Normal Non-cacheable. Why do you still need a DC?

    • @LocutionJulia
      @LocutionJulia 2 роки тому

      No, I believe you are good if your line is non cacheable.