Simple UVM Testbench, from Spec to Testbench (ALU Verification with UVM)

[@saibatapasen433]

Hey, please continue making more such videos. Its really helpful for the student community

[@pritikarout-ur9xt]

Really for beginner level ur explanation is awesome. Thank you for sharing ur knowledge😊

[@soumyaranjandash4188]

Nice demonstration! Please post more videos on projects related to UVM. Good luck!

[@boru4509]

Thanks for the video. Looking forward to seeing upcoming ones. 👍

[@GARVITVYAS-s3s]

Thanks a lot, very helpful video and amazing explanation. Please add more such videos for Verification with UVM for ALU2.0, etc.
Appreciate the effort!

[@Carlosramirez-he4zi]

This video is a GODSEND

[@narasimhaswamy7986]

Thanks !! u made the TB creation so easy

[@dikshabodake-k1k]

Your videos are excellent.. please make videos on AXI, APB and constraints as well

[@anuragvarshney6892]

Excellent video with crystal clear coding from scratch...Thanks very much for this helpful video..Scoreboard part was very useful...
Please post video on how to integrate UVC and use of virtual sequence and virtual sequencer

[@vishal_moladiya_music]

Very much helpful video for begginers. Especially Scoreboard part was very good.
Please make some video on protocol like APB or AHB or AXI VIP

[@akankshathirupathi5934]

Excellent video please make more videos.

[@sayadislam2809]

Thanks man, this is so helpful.

[@JNECLatheshav]

❤excellent teaching

[@abhiramkumar_DV]

waiting for more practical testcase scenarios😇

[@verif_engg_vlsi6754]

Indeed it was really helpful especially SB.
Please try to make another video on Scoreboard.

[@shashvatmaurya6791]

Thanks a lot...please make a video on APB or AXI also.

[@YashiAkhtar-ri7ck]

Thanks !! u made the TB creation so easy 🙂 looking forward for next videos

[@Shrawankumar-oc2vj]

Thanks for sharing ☺️.
Waiting for new videos.

[@anand_kumar8405]

Great sir please post more videos related to uvm project like amba family i2c protocol

[@אופירבניטה]

you create handle to sequence_item in scb which is curr_trans but you dont create object with type id method can you explain why

[@sabarish862]

Great Video!

[@abhiramkumar_DV]

Thanks a lot Sir. 😊

[@sandeepprabhakaran7920]

Nice video. Please make more of these type. Quality could be little high.

[@ivanmilin32]

Hi, will you soon post video where you explain what's happening in report?
Thanks !

[@indiandrums8591]

Hi sir , How can curr_state store a pop_front value ...here we have not used create method to assign memory to the handle "curr_state"

[@steliossideris6498]

Do you have a suggestion for the next video.?

[@chetu1991]

Very useful. Please make a video on APB to AHB bridge, thank you...

[@shuvambiswas458]

Hey i am learning uvm_verification can you share some material how we can verfy the whole cpu . I have designed the whole MIPS processor for some certain instruction. that processor i want to verify

[@SamalaRahul-n5l]

Thank you for your valuable time spent on this videos for us, Am an RTL Verification Enginner without project, I want real work knowledge on this, can you help me sir.

[@placeholder5982]

Why was "bit" used for CarryOut? It's a 2 state type right?

[@LulusCastle]

can u share video about uvm constructor in detail

[@HimanshuMadnani]

how are you "reset" directly in sequence.sv? Shouldnt' it be seq_item_packet.reset?

[@HimanshuMadnani]

using*, and not using parameter in uvm_sequence class...uvm_sequence#(req,rsp)

[@Carlosramirez-he4zi]

When is the next video coming ???????

[@kamranrasheed4180]

The task compare has case logic for ALU , what logic should be used in case for pcie?

[@lancelotrampaculan2075]

Where is the next video wherein he will show what he sees when he simulate this?

[@ajgameryt9658]

please make a AXI video for UVM TB

[@durgamveena6147]

Hi, can you please say in which component you have written "vif" which is declared in TOP module

[@sukanyadeshamukhya1158]

Could you please make some videos on ubus?

[@kamranrasheed4180]

Why are the DUT and Interface signals different?

[@asiclab40519]

DUT and Interface signals can be different. They are different entities that are connected together. So. names does not matter.

[@efeberkayyitim2435]

Will there be a sequel video?

[@anand_kumar8405]

Hi sir make video for ral model

[@ClaphamLouise-u1s]

Kristopher Wall

[@GimmeLove]

I have one question: Does he hate his keyboard? 🤔 😂

[@KellySyverson-v2m]

Perez Brian Gonzalez Sarah Clark Angela

[@WallaceAubrey-b2m]

White Mark Hernandez Linda Thomas William

[@AliciaRannels]

7771 Zackary Neck

[@AlsoppHilda]

Jones Jessica Harris Frank Walker Larry