Hi, I was just rewatching this and it seems to me that you may have edge vs. level triggered swapped 1:05. I believe the first example is actually level triggered and the master/slave design makes it edge triggered (which I believe is the purpose of M/S). All sources seem to agree. Here's one result of a quick search - Thanks! "Conventional J-K master-slave flip-flops are properly called "pulse-triggered" or "level-triggered". On the other hand, a D master-slave flip-flop is edge-triggered, because the D input and its complement always drive the master stage in complementary fashion, even while the clock is high"
I believe what I said is accurate. In the referenced text both are master-slave flip-flops. As you know these are basically built with two JK flips flops. I was saying that a regular JK flip-flop that is triggered with a short pulse is edge-triggered. The Conventional J-K master-slave flip-flops is what I was calling level-triggered. I did not realize that a D master-slave flip-flop is edge-triggered but I suppose that is correct.
@@GlobalScienceNetwork Do you agree with the following? "The J-K input data is loaded into the master while the clock is high and transferred to he slave and the outputs on the high-to-low clock transition" (Source is sn74ls107a.pdf)
@ScienceNetwork We might be agreeing without actually knowing that we are. Do you agree with the following? (from EE stack exchange, also the SN74107 datasheet seems to agree), Basically it is saying that it is a positive pulse triggered flip flop. "The M-S JK flipflop is not edge triggered, it is pulse triggered. What you have discovered is a phenomenon which M-S JK flipflops suffer from known as 'ones catching'. This is when noise on the J or K inputs whilst the clock is high can alter the resulting outputs of the flipflop. To avoid this drawback of the M-S JK flipflop the clock pulses should be kept short or avoid Master-Slave flipflops altogether and use true edge triggered ones."
@@Enigma758 The M-S JK flip flop is pulse-triggered or level-triggered I agree with that. However, I think the noise is on the regular edge-triggered JK flip-flop. If you watch my video called "D Flip Flop and JK Flip Flop" at 7:32 it shows the racing condition where the output toggles when a large capacitor is used. I am not positive this is what you are referring to as 'ones catching' but it is a racing condition. The MS JK flip flop solves the problem with the racing condition/noise because you need a full rise and fall of the clock signal before it changes value. The MS JK flip-flop timing is half the clock signal which can be used as a frequency divider. The reason this is good is that if there is noise on the high signal the output will not change states until it goes to a full low value. So the MS-JK flip-flop is the solution. Otherwise, we could have built the flip-flops/registers with about half as many transistors which would be nice. This is why most flip flops are master-slave JK flip flops. On my computer build I just used the the regular JK flip flop for the counters and it worked fine because I sent a short pulse duration. This reduced the transistor count significantly. You do have to make sure the timings of the registers are in sync as the event change is at the falling edge of the clock for the master-slave JK flip-flops.
@@GlobalScienceNetwork Yes, I think we are in agreement on that. I think the MS FF is somewhat analogous to a pawl and ratchet that must first engage, then disengage from the gear to advance a single step. One reason I'm interested in this is to build a practical divider for a transistor clock. I tried simulating the simpler (RC differentiator) version in falstad, but it still suffers from the race condition, but it's clear that it works for you in practice so I should just try building one myself.
Hi, I was just rewatching this and it seems to me that you may have edge vs. level triggered swapped 1:05. I believe the first example is actually level triggered and the master/slave design makes it edge triggered (which I believe is the purpose of M/S). All sources seem to agree. Here's one result of a quick search - Thanks!
"Conventional J-K master-slave flip-flops are properly called "pulse-triggered" or "level-triggered". On the other hand, a D master-slave flip-flop is edge-triggered, because the D input and its complement always drive the master stage in complementary fashion, even while the clock is high"
I believe what I said is accurate. In the referenced text both are master-slave flip-flops. As you know these are basically built with two JK flips flops. I was saying that a regular JK flip-flop that is triggered with a short pulse is edge-triggered. The Conventional J-K master-slave flip-flops is what I was calling level-triggered. I did not realize that a D master-slave flip-flop is edge-triggered but I suppose that is correct.
@@GlobalScienceNetwork Do you agree with the following?
"The J-K input data is loaded into the master while the clock is high and transferred to he slave and the outputs on the high-to-low clock transition"
(Source is sn74ls107a.pdf)
@ScienceNetwork We might be agreeing without actually knowing that we are. Do you agree with the following? (from EE stack exchange, also the SN74107 datasheet seems to agree), Basically it is saying that it is a positive pulse triggered flip flop.
"The M-S JK flipflop is not edge triggered, it is pulse triggered.
What you have discovered is a phenomenon which M-S JK flipflops suffer from known as 'ones catching'.
This is when noise on the J or K inputs whilst the clock is high can alter the resulting outputs of the flipflop.
To avoid this drawback of the M-S JK flipflop the clock pulses should be kept short or avoid Master-Slave flipflops altogether and use true edge triggered ones."
@@Enigma758 The M-S JK flip flop is pulse-triggered or level-triggered I agree with that. However, I think the noise is on the regular edge-triggered JK flip-flop. If you watch my video called "D Flip Flop and JK Flip Flop" at 7:32 it shows the racing condition where the output toggles when a large capacitor is used. I am not positive this is what you are referring to as 'ones catching' but it is a racing condition.
The MS JK flip flop solves the problem with the racing condition/noise because you need a full rise and fall of the clock signal before it changes value. The MS JK flip-flop timing is half the clock signal which can be used as a frequency divider. The reason this is good is that if there is noise on the high signal the output will not change states until it goes to a full low value. So the MS-JK flip-flop is the solution. Otherwise, we could have built the flip-flops/registers with about half as many transistors which would be nice. This is why most flip flops are master-slave JK flip flops. On my computer build I just used the the regular JK flip flop for the counters and it worked fine because I sent a short pulse duration. This reduced the transistor count significantly. You do have to make sure the timings of the registers are in sync as the event change is at the falling edge of the clock for the master-slave JK flip-flops.
@@GlobalScienceNetwork Yes, I think we are in agreement on that. I think the MS FF is somewhat analogous to a pawl and ratchet that must first engage, then disengage from the gear to advance a single step. One reason I'm interested in this is to build a practical divider for a transistor clock. I tried simulating the simpler (RC differentiator) version in falstad, but it still suffers from the race condition, but it's clear that it works for you in practice so I should just try building one myself.
i was just plannig on building something like this! thanks for this video:D
Sure thing, thanks for watching!
Are you using BJT's or FET's in your circuit?
These are 2N2222 or 2N3904 NPN BJT's. I was thinking about trying 2N7000 n-FET to build similar circuits.