How do you get /sim_snn_rgb/duv/output0/sum to display in the Wave view window of Questa Intel Starter (6:42 mark in video)? I can get many of the other signals to display after running the simulation, but not all the ones you show. Also I don't have the sections (RGB In, RGB Out, and Neuron Out 0) on the left size of the Wave window like you have. How did you get those to display like that? Thanks for the video's they were really helpful!
On compilation, there is a setting to keep the visibility of all internal signals. At 5:00 there is at the top of the window the menu item "simulate". There you find "Design Optimization" and then "Visibility". Hope this solves the issue.
@@marcowinzker3682 thanks, now I can get sum to display on the Wave window, but it is rendered as just a number (series of number blocks). How do you get sum row to display as a graph?
@@dukecitywildcat In the waveform window you select the signal and with right-click define the radix (e.g. decimal, unsigned). Then you right-click and go to format -> analog.
Prof, It works fine with questa, but if we want to run on vivado, it did not work when run as it is, is there any changes to do or any ways to produce bitstream as our aim is to run on fpga
I have used several FPGA design flows in the past, and Xilinx is high quality provider. But of course there are small differences in interpretation of VHDL code. I did not check this design with Vivado. My suggestion to you: Please check all warnings of the compilation. Often there are hints. You can also compare the results of Questa and Vivado. How many FPGA elements do they use? How many for each submodule? If there are huge differences, part of that code is interpreted differently.
Interesting question! As the neural network has a hidden layer, an xor should be no problem. You could use training data with xor-characteristics and see how training handles that. I will also have a look into it.
@@marcowinzker3682 for an xor NN we have weights and 2 biases and input data 00,01,10,11. In fact I have a trained NN , now I wanna implement it in vhdl. I think we have to write a package for each neuron. Please let me know. thanks a lot.
Hey prof. I'm also interested in the implementation of a neutral network in FPGA. In fact I would like to know how generate VHDL code a particular trained neural network. I'm looking forward to hearing from you
@@wachirakaburu2332 The video "Machine Learning on FPGAs: Advanced VHDL Implementation" explains VHDL generation from Octave. ua-cam.com/video/CoyhAqUS2f0/v-deo.html
![FPGAs are (not) Good at Deep Learning [Invited]](http://i.ytimg.com/vi/WWCWsub3YkE/mqdefault.jpg)
Prof, thank you for putting up these work. Your channel is golden!
How do you get /sim_snn_rgb/duv/output0/sum to display in the Wave view window of Questa Intel Starter (6:42 mark in video)? I can get many of the other signals to display after running the simulation, but not all the ones you show. Also I don't have the sections (RGB In, RGB Out, and Neuron Out 0) on the left size of the Wave window like you have. How did you get those to display like that? Thanks for the video's they were really helpful!
On compilation, there is a setting to keep the visibility of all internal signals.
At 5:00 there is at the top of the window the menu item "simulate". There you find "Design Optimization" and then "Visibility".
Hope this solves the issue.
@@marcowinzker3682 thanks, now I can get sum to display on the Wave window, but it is rendered as just a number (series of number blocks). How do you get sum row to display as a graph?
@@dukecitywildcat In the waveform window you select the signal and with right-click define the radix (e.g. decimal, unsigned). Then you right-click and go to format -> analog.
Thank you, Professor.
Prof, It works fine with questa, but if we want to run on vivado, it did not work when run as it is, is there any changes to do or any ways to produce bitstream as our aim is to run on fpga
I have used several FPGA design flows in the past, and Xilinx is high quality provider. But of course there are small differences in interpretation of VHDL code.
I did not check this design with Vivado. My suggestion to you:
Please check all warnings of the compilation. Often there are hints.
You can also compare the results of Questa and Vivado. How many FPGA elements do they use? How many for each submodule? If there are huge differences, part of that code is interpreted differently.
Prof, I run it on vivado successfully~@@marcowinzker3682
Any specific reason for using matlab/octave and Quartus instead of Vivado?
We are using Intel FPGAs in our lab. Other FPGA providers are also offering good products.
Hi prof, please implement a neural network of xor in vhdl. Thank you.
Interesting question!
As the neural network has a hidden layer, an xor should be no problem. You could use training data with xor-characteristics and see how training handles that.
I will also have a look into it.
@@marcowinzker3682 for an xor NN we have weights and 2 biases and input data 00,01,10,11. In fact I have a trained NN , now I wanna implement it in vhdl. I think we have to write a package for each neuron. Please let me know. thanks a lot.
Hey prof. I'm also interested in the implementation of a neutral network in FPGA. In fact I would like to know how generate VHDL code a particular trained neural network. I'm looking forward to hearing from you
@@wachirakaburu2332 The video "Machine Learning on FPGAs: Advanced VHDL Implementation" explains VHDL generation from Octave. ua-cam.com/video/CoyhAqUS2f0/v-deo.html
Hello Prof., i would like to start working with DNN in FPGA, can you suggest me good latest board.