𝐖𝐢𝐫𝐞 𝐋𝐨𝐚𝐝 𝐌𝐨𝐝𝐞𝐥 (𝐖𝐋𝐌) 𝐢𝐧 𝐒𝐓𝐀/𝐕𝐋𝐒𝐈 | 𝐰/ 𝐄𝐱𝐚𝐦𝐩𝐥𝐞𝐬 |

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  • Опубліковано 29 січ 2025

КОМЕНТАРІ • 6

  • @harshitsingh480
    @harshitsingh480 2 роки тому

    your videos are very good and nice. i got to know about unate and wire load model

  • @harshitsingh480
    @harshitsingh480 2 роки тому +1

    ​can you help you in rtl to gds flow of round robin arbiter design by giving power analysis timing and area analysis too on vivado? also placement and routing layout basically if you can give a full video of how rtl to gds with placement layout and routing is done in one video it will be helpful for us to understand the flow and learn vivado tool also just one question can no of bits we can increase in that a bit of idea also if in video you can give

    • @vlsiexcellence
      @vlsiexcellence  2 роки тому

      Hi @Harshit, Will try to cover in some of the future videos. Thanks for the feeback.

  • @huhuu-mq1tx
    @huhuu-mq1tx 11 місяців тому

    hi sir, can you help to explain how slack in pt_shell relates to the lib time in etm libs? i dont quite understand.
    loading up a pt_shell takes time, so i would really like to debug the slack from the etm libs instead as we can open the etm lib in a text editor to see the values of delay..thanks

    • @huhuu-mq1tx
      @huhuu-mq1tx 11 місяців тому

      i eman how does cell_Rise/rise_constraint/fall_constraint in etm related to the slack in pt_shell