I apologize for the delay in responding. PAL is similar to ROM which stores data in the form of 0s and 1s. In our case, [A B C D] represents the address and [w x y z ]are data bits in each memory location. In this question, the memory data are represented in the form of minterms ( for address ABCD= [0 0 0 0] respective data in that location is wxyz=[0 0 1 0])
If the number of minterms is 3 or fewer, you can implement it using one standard structure consisting of 3 AND gates and 1 OR gate. However, if the minterms exceed 3, you can split the expression into groups of 3 minterms and assign a temporary variable. Then, you can use 2 or more standard structures and connect them using feedback. Example: x= ac+bc+ab+ad+abc let f = ac+bc+ab (implement using a standard structure) x= f+ad+abc (where f is feedback of already implemented structure )
In the standard PAL structure, I have assumed 3 product terms (3 AND gates and one OR gate). That's why I grouped the terms into groups of 3. If you consider a standard structure with 4 product terms, then you would need to form groups of 4.
In this example, standard PLA consists of 3 AND gate followed by an OR gate. However, for the expression w and x, which has 2 minterms terms, that's why we made 3 and 6 untouched. In a PLA, while the physical structure remains fixed, users can program or configure the connections between the inputs, AND gates, and OR gates based on their desired logic function.
The standard PLA structure has a fixed format. In our case, we considered using 3 AND gates followed by one OR gate. However, since we have an expression with 4 minterms, it's not possible to implement it with just 3 AND gates. Therefore, we split the expression and created a feedback loop.
Thanks for excellent teaching.. it is so helpful for the semester exam❤ thanks a lots sir
Your explanation is so amazing
Thank you sir you are explaining it better then our professor 😂❤
Finally I understood ......tqs..
this video is awesome.
Excellent!
Awesome sir
great explaination
why we are programing the ANG gate by Dot instead of Cross cause generally it means as it's fixed not programmable right?
How did you get the numbers you added to the k map when generating the PAL
At what time duration in the video you are having doubt?
EC Learn 1:12s while you were writing the Boolean functions didn’t understand how you got the numbers £ 2,12,13
I apologize for the delay in responding. PAL is similar to ROM which stores data in the form of 0s and 1s. In our case, [A B C D] represents the address and [w x y z ]are data bits in each memory location. In this question, the memory data are represented in the form of minterms ( for address ABCD= [0 0 0 0] respective data in that location is wxyz=[0 0 1 0])
Sir if there is no common terms then what we have to do sir
If the number of minterms is 3 or fewer, you can implement it using one standard structure consisting of 3 AND gates and 1 OR gate. However, if the minterms exceed 3, you can split the expression into groups of 3 minterms and assign a temporary variable. Then, you can use 2 or more standard structures and connect them using feedback.
Example:
x= ac+bc+ab+ad+abc
let f = ac+bc+ab (implement using a standard structure)
x= f+ad+abc (where f is feedback of already implemented structure )
@@eclearn2270 can you explain with a video without common terms sir please 🥺🙏🏽
22:26 sir i have a doubt that why r u taking w as a feedback ?
For x
why we make pair of 3 in table like 1 2 3 and then 4 5 6
?
In the standard PAL structure, I have assumed 3 product terms (3 AND gates and one OR gate). That's why I grouped the terms into groups of 3. If you consider a standard structure with 4 product terms, then you would need to form groups of 4.
Why do we create this table can't we make it directly to the circuit after Boolean expression has found
🙂
dude you are awesome thanks
why did we use the feed back with w i don't get it
Thank you so much brother❤❤❤
Sir why 3rd and 6th product term is taken in the table.can we ignore it as it is not there
In this example, standard PLA consists of 3 AND gate followed by an OR gate. However, for the expression w and x, which has 2 minterms terms, that's why we made 3 and 6 untouched. In a PLA, while the physical structure remains fixed, users can program or configure the connections between the inputs, AND gates, and OR gates based on their desired logic function.
thanks❤
Thank you so much
Thankyou Sir 😢🎉
thanks a lot sir
Thanks brother❤
Tq sir ❤
Why to take feeback??
The standard PLA structure has a fixed format. In our case, we considered using 3 AND gates followed by one OR gate. However, since we have an expression with 4 minterms, it's not possible to implement it with just 3 AND gates. Therefore, we split the expression and created a feedback loop.
👍
can u help me?? ı have question about Eprom