HWN - Digital/Analog Design Interview Question
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- Опубліковано 20 вер 2024
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Excellent. Many confusions solved in a single question.
Thank you so much! We saw your argument with "Aspect" in the comments. We wanted to clarify that for PMOS devices the source is always at a higher potential than the drain and for NMOS devices the opposite is true. Thank you for being here!
Seems like he deleted his comment as he was obviously confused. Lol
current should flow from 5V to 3V ( higher potential to lower potential ) . Hence calculation should be from right (NMOS ) to left ( PMOS ) . isn't it ?
There is no way Vz > 5V.
Thé NMOS with 4V gate voltage is exactly at vgs=vth so you definitely have some conductivity in practice while the NMOS with 2V gate voltage has vgs
Sir ! So you mean that the vz=3v,vy=1v,vx=3v
Right??🤔
I would have asked, gate voltage referred to what node ? GND ? Drain/source ?
Vx=3V, Vy=3V, 1
To keep all devices in conduction, we -infinity
Absolutely amazing!!
Are you serious? There are some wrong pre-assumptions here. Even if to assume that the devices and connectivity are all ideal (why intermediate caps then?) they are still at least four terminal devices, with diodes excluding at least one infinity scenario per device type. So this is already wrong. Then, the very first two questions should sound like "is it standard CMOS with the wells controlled by DC voltages? Are all depicted voltages ideal DC voltages?" If both answers are "yes", we don't care about Initial intermediate nodes voltages as it is clear that the devices are ideal and it is a DC or DC-like case (time, current and capacitance values are not given, so time domain waveforms can't be asked for either). So, either the formulation of the task is not proper or the one who passed the story from the interviewer messed it up.
Dmitri, thank you for being here! You have just demonstrated how this question can (and will) be used to test both recent college grads as well as experienced engineers (which you seem to be). We're here to introduce the topics to interviews. Depending on the experience of the applicants, one can decide to push further or dial it back. Let us know if you agree with that. Cheers!
@@HardwareNinja you are welcome. Glad that you teach younger generations. Keep Up. To bei frank, I don't even know what triggered me more, poor formulation or the task itself. Somehow I feel sorry for young engineers when they get interviewed like that.
@@dmitria6847 We do see a difference between Europe and America in terms of education and what's expected to be "basic knowledge". That is why questions will vary. We think a good question should establish a baseline of knowledge for all candidates. Then, depending on knowledge and ability of the candidate the question can be expanded. We believe this was the aim of the original interviewer with this one. We cannot possibly know but we like to give them the benefit of the doubt :)
Can we use superposition like first case is 3V is there but 5V is grounded and second case is there is 5V and 3V is grounded?
Hi Ritayan, were not sure what you're referring to here. But like with any problem, there are always multiple ways of solving it
@Hari Maddukuri Thanku for the point. So if we consider the small signal circuit of a mos, then can we apply superposition.
@Hari Maddukuri yah I know it's of no use in this qn. I asked in general
Hi Ritayan, are you getting same results after using superposition?
really nice video! Thank you
But for any current to flow through the pmos and nmos don't we need |Vgs| > |Vth|?
You're correct! The source of the device (whether PMOS or NMOS) changes depending on the potential. You can always double check |Vg - Vs| >= |Vth| for all the assumptions that were made.
Keep an eye on changing source and drain terminals along the analysis bro. For MOSFETs source and drain are not fixed unlike emitter and collector in BJT
I would ask which side is S and which is D of each MOSFET since they are symmetric as drawn.
shouldnt be asking that.MOSFET is a symmetric device and there is no difference bw s and D ..whichever is higher potential should be considered D
Very good video
What if the gate voltage of first Pmos is +3 V instead of the 1V now, then what's Vx, can u please tell.
Assuming Vx started from + infinity,it will act as source...and device will be on till Vx=4V(Vsg=1V)
The solution and explanation is incorrect on so many levels Ninja. Verify your concepts and then upload videos. College students will learn and remember false basic concepts. Please Take care.