I find a large amount of information on cache behavior on the read side, but I would like to hear more about the behavior of multilevel cache on the write-store side of the cpu. When is the new data availible to reuse in the same core or a different core on the same package, is there any need to wait for the line of data to flush to main memory before reading it from shared cache, is it purely in L1d or simultaneously copied to L2 L3?
It depends on the cache protocol: some protocols won't write data directly to main memory unless another core/thread asks for it. This is done for performance reasons: if no other thread needs that data, there's no need to waste cycles writing to main memory. The same applies for intermediate caches: when reading data from main memory, it's usually copied to L2 and L1 (L3 if present). At some point some data might be evicted from L1, but because L2 is bigger it might still be present in L2. So next time you read that same data (provided it hasn't been modified by another thread), it will be read from L2. There are other behaviours as well though: you might have a write through cache, so that when modifying a piece of data, it goes straight to main memory without touching the intermediate caches. If you need to read back that data, you will have to wait for main memory. To learn more about cache coherency protocols, this is a good starting point: en.wikipedia.org/wiki/MESI_protocol. This course also good lectures on cache coherency: 15418.courses.cs.cmu.edu/tsinghua2017/
Great talk!
Really good talk, thanks!
Nice talk! Thank you!
I find a large amount of information on cache behavior on the read side, but I would like to hear more about the behavior of multilevel cache on the write-store side of the cpu. When is the new data availible to reuse in the same core or a different core on the same package, is there any need to wait for the line of data to flush to main memory before reading it from shared cache, is it purely in L1d or simultaneously copied to L2 L3?
It depends on the cache protocol: some protocols won't write data directly to main memory unless another core/thread asks for it. This is done for performance reasons: if no other thread needs that data, there's no need to waste cycles writing to main memory. The same applies for intermediate caches: when reading data from main memory, it's usually copied to L2 and L1 (L3 if present). At some point some data might be evicted from L1, but because L2 is bigger it might still be present in L2. So next time you read that same data (provided it hasn't been modified by another thread), it will be read from L2.
There are other behaviours as well though: you might have a write through cache, so that when modifying a piece of data, it goes straight to main memory without touching the intermediate caches. If you need to read back that data, you will have to wait for main memory.
To learn more about cache coherency protocols, this is a good starting point: en.wikipedia.org/wiki/MESI_protocol. This course also good lectures on cache coherency: 15418.courses.cs.cmu.edu/tsinghua2017/
where can i find the slides for this talk? they are not present in the github