sir i was using synopsys custom compiler, and the uncox upcox values were different.i am facing two issues.if i am keeping the supply vdd as 1.8v then seeing some mos are not in saturation. one more thing is the tail current source mos current number are not matching even though the vgs is same, basically in the current mirror circuit both the mos are having different current.any suggestions
thank you for the video , i will use it in my future homework and projects , i really learned allot from you , thank you for the design steps , im looking forward to learn from more of your good work , best regards
Hello sir, to find W/L ratio of transistor M3 and M4 we went through simulation and for M1 and M2 we are going through different approach(using transconductance),why we can't go by same approach like M3 and M4. plz clear it
Why you are giving input to one of the mosfet only in ac analysis For differential amplifier same should be given in 180 degree phase to another one also naa. Correct me if i am wrong
Informative tutorial Thanks a ton. For the same design values my MOS are in triode region any tips?. I have a doubt of why there is a current value in VDD.( @6.39 sec)
+sreerej1 How do you say KVL ? I dont get how he would come up with that equation using KVL, could you explain a bit more ? Vin is not connected to the circuit at all since the gate is high impendance and thus can be considered to be open circuited, badly want to know how this equation fits here though KVL, would be great if you could help a bit more :)
This discussion was 2 years ago, but i would like to answer. Vin should be greater than 0.8 w.r.t ground. from the gate of M1 i.e vin to ground should be greater than 0.8V. there are two voltage drop point between vin and ground which is Vgs1 and Vds5. since Vin should be greater 0.8V vin >Vgs1 +Vds5. hope u understand.
@@bhuvi441 Let's discuss in a general way: Vin2=Vg2 Vs2=Vds5 Vgs2=Vg2-Vs2 Vgs2=Vin2-Vds5 Vin2=Vgs2+Vds5 Vin2>=Vgs2+Vds5 (Because the video has considered the minimum value here 0.8v, so either 0.8v or more) Please correct me, because it's just my assumption.
It's been very long since the last video is uploaded. Could you please continue uploading such videos? Thanks
thanks a lot sir.. it was very easy only due to your way of teaching
Hello sir,
All videos r really very informative.
I'm eagerly waiting for the next videos .
Thank you very much.
Where did things go wrong??
Hi Hafeez, your videos are really useful for a beginner to learn Analog Design methodology. Can you discuss how to design a simple LDO? Thanks :-)
Hello Sir,
All the videos are excellent.....I am really happy to listen you lecture.....Thank You sir for giving such nice design methodology....
thank you it is very good and easy to understand
sir i was using synopsys custom compiler, and the uncox upcox values were different.i am facing two issues.if i am keeping the supply vdd as 1.8v then seeing some mos are not in saturation. one more thing is the tail current source mos current number are not matching even though the vgs is same, basically in the current mirror circuit both the mos are having different current.any suggestions
Thank you very much hafeez,....These videos are really awesome and extremely helpful.
I like your tutorial. It is much better than the one in cmos.edu
thank you for the video , i will use it in my future homework and projects , i really learned allot from you , thank you for the design steps ,
im looking forward to learn from more of your good work ,
best regards
Thankyou sir.....can design Latched comparator w and L values
Hello sir, to find W/L ratio of transistor M3 and M4 we went through simulation and for M1 and M2 we are going through different approach(using transconductance),why we can't go by same approach like M3 and M4. plz clear it
Why you are giving input to one of the mosfet only in ac analysis
For differential amplifier same should be given in 180 degree phase to another one also naa. Correct me if i am wrong
Thank you a lot. It is very helpful. Jazak Allah Kheer.
Very Good Tutorial, Thanks
can you plz make 1 video for finding output impedance of a current mirror in mentor or cadence
Great. But, when we use calculator to calculate GBW product, we see rather a different value of GBW. Why is that so?
What is the phase margin for the above circuit?
an excellent video
hi thanks for such a good video. i wanted to ask: i want make gain 15db gain. how can i find w/l, ICMR etc values. thnxs
I really respect you man
Very good tutorial, Thx.
Informative tutorial Thanks a ton. For the same design values my MOS are in triode region any tips?. I have a doubt of why there is a current value in VDD.( @6.39 sec)
Very nice video sir :)
What is the value of vdd?.. Supply voltage at the left of the circuit?.
sir try to design three stage NMC op amp
pls upload two stage design pls ..
At 1:20 , how is Vin > Vgs1 + Vdsat ?? I cant understand this part ! Would be great if someone could help me out !
+Bhuvanesh N apply KVL there..and > sign is, since Vcmr_ is the min common mode voltage than we can apply according to design perspective.
+sreerej1 How do you say KVL ? I dont get how he would come up with that equation using KVL, could you explain a bit more ? Vin is not connected to the circuit at all since the gate is high impendance and thus can be considered to be open circuited, badly want to know how this equation fits here though KVL, would be great if you could help a bit more :)
This discussion was 2 years ago, but i would like to answer.
Vin should be greater than 0.8 w.r.t ground.
from the gate of M1 i.e vin to ground should be greater than 0.8V.
there are two voltage drop point between vin and ground which is Vgs1 and Vds5.
since Vin should be greater 0.8V
vin >Vgs1 +Vds5.
hope u understand.
@@bhuvi441
Let's discuss in a general way:
Vin2=Vg2
Vs2=Vds5
Vgs2=Vg2-Vs2
Vgs2=Vin2-Vds5
Vin2=Vgs2+Vds5
Vin2>=Vgs2+Vds5 (Because the video has considered the minimum value here 0.8v, so either 0.8v or more)
Please correct me, because it's just my assumption.
anyone can provide notes about this calculation
please provide a link to download the cadence tool
Can I get that cadence software for free
Yes. Use vmware
@@KamranKhan-co6ox please how can I get the Cadence Virtuoso software for free for Ubuntu?
@@emmanuelinnocent4505 search on UA-cam cadence free download. There're many videos.
@@HDgaming345 Thank you very much. I'll do that.