Udi FPGA
Udi FPGA
  • 26
  • 7 405
Scatter Gather DMA part2
In this Video I use the Scatter Gather DMA with a xaxidma.h driver.
I use the minimum functions to generate a basic Scatter Gather DMA transaction.
This video is based on my first Scatter Gather DMA video:
ua-cam.com/video/iH_5hE4JdFc/v-deo.html
All the files are in my Github under DMA repository in SGDMA branche
github.com/Udi-FPGA/DMA/tree/SGDMA
Переглядів: 125

Відео

Scatter Gather DMA part1
Переглядів 3252 місяці тому
In this Video I use the Scatter Gather DMA with a simple software. I write directly to the DMA registers and not using xaxidma.h functions. This video is based on my first DMA video: ua-cam.com/video/ELfnMsWiQFQ/v-deo.html the video of saving & rebuilding Vivado project from GIT: ua-cam.com/video/SxiMddNAUkU/v-deo.html
SD card Read & write part2 text
Переглядів 145Рік тому
In this tutorial I show how to read and write from an SD card using software in a Zynq base system. In this Video I show how to Read & write text file from/to the SD card. This tutorial is based on my: DMA basic example video: • DMA basic example and I'm referring to my: Saving Vivado project in Version control video : • Saving Vivado Project in Version control The project is in my GitHub: gith...
SD card Read & write part1 binary files
Переглядів 350Рік тому
In this tutorial I show how to read and write from an SD card using software in a Zynq base system. In this Video I show how to read/write a binary files from/to SD card. This tutorial is based on my: DMA basic example video: ua-cam.com/video/ELfnMsWiQFQ/v-deo.html and I'm referring to my: Saving Vivado project in Version control video : ua-cam.com/video/SxiMddNAUkU/v-deo.html The project is in...
Saving Vivado Project in Version control
Переглядів 884Рік тому
This Video shows how to save a Vivado project in version control. the Project was generated in the SoC APB on ARTY project: ua-cam.com/play/PLv0KRXOsP7Uo8fuF44mrskyqfpQIHuvB_.html The Project files in Github: github.com/Udi-FPGA/SPIvhdl
DMA3-interrupt2
Переглядів 103Рік тому
In this video I run & explain the DMA software in simulation. I run it also on the ARTY board. And tried to run it on the Zynq too.
DMA3-interrupt3
Переглядів 66Рік тому
In this video I explain why the software didn't run straight away on the Zynq. I explain how we chose what part of the system we need to use and how to use them. I fix the software and run it on the Zynq.
DMA3-interrupt1
Переглядів 180Рік тому
In this playlist I show how to use the Xilinx DMA In this video I add Micro-blaze CPU to the simple design in the last videos, and I added interrupt. I prepare the example interrupt DMA software from the Vitis insulation folder to run on the Micro-Blaze system in simulation.
DMA polling software example & using XSCT
Переглядів 331Рік тому
In this video I explain the example software from the last video. I also introduce the XSCT interface, transfer files from my computer to the system and back. I show the XSCT commands: dow -data {file name} {0xaddress} mrd -size b -bim -file {file name} {0xaddress} byte_number
DMA basic example
Переглядів 1 тис.Рік тому
In this Video I build and run a basic DMA design. I explain the basics DMA operation. I build a basic design with a Zynq DMA and a FIFO. I ran the design using the DMA simple polling example from the Vitis installation folder.
SoC with APB bus interface on ARTY part5
Переглядів 2172 роки тому
This tutorial shows how to use an APB bus in Xilinx SoC system This is the fifth Video of 5. In this video, I add constraints, adapt the software for the Zynq, and run the design on the board. all the files are in: github.com/Udi-FPGA/SPIvhdl
SoC with APB bus interface on ARTY part4
Переглядів 1492 роки тому
This tutorial shows how to use an APB bus in Xilinx SoC system This is the fourth Video of 5. In this video I combined the system together, write a simulation software for on the MicroBlaze, and ran a simulation with the software all the files are in : github.com/Udi-FPGA/SPIvhdl
SoC with APB bus interface on ARTY part3
Переглядів 1642 роки тому
This tutorial shows how to use an APB bus in Xilinx SoC system This is the third video of 5. In this video I generate a register file and build the full modules for the system all the files are in : github.com/Udi-FPGA/SPIvhdl
SoC with APB bus interface on ARTY part2
Переглядів 4892 роки тому
This tutorial shows how to use an APB bus in Xilinx SoC system This is the second Video of 5. In this video I build the SPI master & slave modules to have peripherals in the system all the files are in: github.com/Udi-FPGA/SPIvhdl
SoC with APB bus interface on ARTY part1
Переглядів 3092 роки тому
This tutorial shows how to use an APB bus in Xilinx SoC system This is the first Video of 5. In this video I generate the SoC system with the APB bridge all the files are in : github.com/Udi-FPGA/SPIvhdl
ARTY Linux Video 6 - Linux application.
Переглядів 2512 роки тому
ARTY Linux Video 6 - Linux application.
ARTY Linux Video 5 - Generation Linux operating system
Переглядів 3162 роки тому
ARTY Linux Video 5 - Generation Linux operating system
ARTY Linux Video 4 - FPGA design
Переглядів 2822 роки тому
ARTY Linux Video 4 - FPGA design
ARTY Linux Video 3 - petalinux installation
Переглядів 4712 роки тому
ARTY Linux Video 3 - petalinux installation
ARTY Linux Video 2 - Ubuntu installation
Переглядів 2522 роки тому
ARTY Linux Video 2 - Ubuntu installation
ARTY Linux Video 1 - Introduction
Переглядів 3752 роки тому
ARTY Linux Video 1 - Introduction
Nios Soc Course part5
Переглядів 713 роки тому
Nios Soc Course part5
Nios Soc Course part4
Переглядів 763 роки тому
Nios Soc Course part4
Nios Soc Course part3
Переглядів 793 роки тому
Nios Soc Course part3
Nios Soc Course part2
Переглядів 1193 роки тому
Nios Soc Course part2
Nios Soc Course part1
Переглядів 2703 роки тому
Nios Soc Course part1

КОМЕНТАРІ

  • @michaelzemah1476
    @michaelzemah1476 6 днів тому

    Hi Udi, Does all the steps for creating the petalinux kernel the same when using WSL? (it should be an ubuntu distro by default). Also, can you try making a tutorial developing C/C++ linux app in VS-Code and WSL ? and debugging the target with gdb-server on the Zynq ? I think it would be great...

  • @NorbertNipken
    @NorbertNipken Місяць тому

    RIP to your ENTER button. 😅

  • @michaelzemah1476
    @michaelzemah1476 Місяць тому

    Finally !! looked for a tutorial like this a while now !! Can you make an example with DMA in circular mode, using interrupts to accomplish double buffer mechanism ??? can be used for DSP applications...

    • @Udi-FPGA
      @Udi-FPGA Місяць тому

      I show Interrupt handling in tree videos I did for DMA-interrupt1;2;3. For circular mode you first need to do the Scatter Gather mode. This mode have cyclic option I may do a tutorial on it in the future.

  • @akhilakki8555
    @akhilakki8555 Місяць тому

    Hi can u send code

  • @KellyHornsby
    @KellyHornsby 2 місяці тому

    Hello! Do you have the Vivado project shared anywhere to access? I find the videos to be very helpful. I'm better at the Linux side of things, and not so much at the VHDL side of things. I hope to get an example Vivado 2021.1 project and to use the XSA file from there.

    • @Udi-FPGA
      @Udi-FPGA 2 місяці тому

      Thanks for your comment you shouldn't be afraid from the Vivado. I'm taking you step by step of building the Design. I found an XSA file here forum.digilent.com/topic/19157-vitis-hw-platform-in-arty7-20/ but I'm not shore which version of Vivado was used, and it is very important to much the Vivado version with the Ubuntu version and the PetaLinux version. Thanks Udi

  • @florazhang3995
    @florazhang3995 4 місяці тому

    Thank you! Very helpful tutorial

  • @alfredrose8065
    @alfredrose8065 Рік тому

    Promo-SM ✨

  • @imranhussain-yq2of
    @imranhussain-yq2of Рік тому

    Is it prosible to dump os in board directly and and use this board for verious project

  • @imranhussain-yq2of
    @imranhussain-yq2of Рік тому

    how i dump OS in zedboard or PYNQ Z2 board?

  • @אודיעדני
    @אודיעדני Рік тому

    you can start with my DMA basic example tutorial. there is a link in the buttom

  • @d_registers.h1
    @d_registers.h1 Рік тому

    got this recommended but it's a bit too advanced for my liking, anything you'd recommend for total beginners?

  • @user-arc-givatada
    @user-arc-givatada Рік тому

    עבודה טובה ומקצועית 😊

  • @DongNguyen-qq3in
    @DongNguyen-qq3in Рік тому

    Thank you Edi for sharing! your videos are always helpful to me! Please keep making the new tutorials!

  • @tkgsnkfv
    @tkgsnkfv Рік тому

    Udiiiii How are you? :)

  • @umairsaifullah-e2b
    @umairsaifullah-e2b Рік тому

    Awesome, keeep up the good work, Really appreciating you making these designs. hoping to learn more from you. I am implementing your designs on Eclypse Z7 board.

    • @Udi-FPGA
      @Udi-FPGA Рік тому

      Thank you for your comment. I plan to make more video like this in the future, and I hope you'll find them useful.

    • @gnanapradeep2933
      @gnanapradeep2933 2 місяці тому

      ​@@Udi-FPGAcan you please make a video on zynq ultrascale+ mpsoc.

    • @Udi-FPGA
      @Udi-FPGA 2 місяці тому

      @@gnanapradeep2933 I wish I Could I need an zynq ultrascale+ mpsoc at home for this. (I'm doing my Videos at home) but I work with mpsoc at work and it is exactly the same. just that the mpsoc have 6 cores and the zynq7000 only 2. once you put your zynq in the Block design and add something (like DMA) the Autoconnection will work the same.

  • @DongNguyen-qq3in
    @DongNguyen-qq3in 2 роки тому

    Hi Udi, your tutorial is brilliant and it is really helpful for beginners like me. I have been struggling to do linux set-up in virtual machine, petalinux installation, and build a linux project for Zynq device. Thank you for the these video serries. I have a question. I followed your tutorial and have a SDcard ready. However, when I insert the SDcard in ARTY Z7 board, it keeps asking me to login. I do not know what are they? do you have any idea about that? Thank you and happy new year!

    • @Udi-FPGA
      @Udi-FPGA 2 роки тому

      Hi Dong Thank you for your nice comment. I did those tutorials to help you and other like you. For your question: I can thing of two options why the Linux askes for user and password. I saw Linux distributions which asked this and the user's name & password were 'root'. (User-name: root and password: root). But as you can see in my videos this wasn't the case when I installed my Linux. Another option is that you forgot to add boot.scr file to your SD-card. This happened to me in the first times I did this. This file is a new addition to the Xilinx Petalinux and wasn't in previous versions of Vivado/Vitis/Petalinux. I hope this is useful to you, and again thank you for your comment.

    • @DongNguyen-qq3in
      @DongNguyen-qq3in 2 роки тому

      @@Udi-FPGA Hi Udi, Thank you for your prompt reply. I did add the scr file into SDcard and also tried root:root as username:password but none of them works. it is weird, isn't it?

    • @DongNguyen-qq3in
      @DongNguyen-qq3in 2 роки тому

      @@Udi-FPGA Dear Udi, i found the reason for my problem. I used petalinux 2022.1 and and for the first time, I have to enter the petelinux as username, then it will ask me to set a new password. cheers! Dong

    • @Udi-FPGA
      @Udi-FPGA 2 роки тому

      @@DongNguyen-qq3in Hi Dong I’m glad you succeeded in working this out. I say many times in the tutorial to keep Vitis/Vivado & Petalinux in the same version. In the first video you can see that I go to a lot of troubles to match the Ubuntu version to the Vitis/Vivado/PetaLinux version. Good for you and have the best luck. 👍

  • @Rysino
    @Rysino 3 роки тому

    Noise od great. But why not implement own core? ;)

    • @Udi-FPGA
      @Udi-FPGA 3 роки тому

      This problem is from ASIC design. When designing an ASIC, we use to prototype the ASIC on FPGA, until the ASIC is ready (which an be a year or more from now). For that we start implementing the Verilog code on an FPGA, check it in high speed and even write software for the ASIC which will be here a year or more from now. Most of the Verilog code for the ASIC is peripherals. The ASIC CPU can a third-party CPU (like ARM or ARC) but we develop the peripherals, so I don't need the real CPU we just need a CPU which can do reads & writes from the code. The Nios II do this nicely if we just have a comfortable bridge. And this is what, I was trying to show in this video.