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100RandomTasks
Приєднався 10 кві 2011
Electronics and other interesting things that I like to talk about.
HOW TO CREATE A CPU IN AN FPGA - Part 9 - Top Down BOOT
TOP DOWN CPU
This video prepares the CPU for the addition of the stack by altering the design to load the start address of the program from the top 2 bytes of the memory address space.
The circuit is also updated and includes a 2k ROM, 4 line to 16 line decoder to break up the address space into 4k blocks and has the original 8 bit output port as before.
A 2k RAM will be added in the next video for the stack access.
Thanks to everyone who've stuck around for this series! More videos to come. Please subscribe so you don't miss them.
Cheers.
Propeller EEPROM Programmer:
ua-cam.com/video/L7MCQwWsKGw/v-deo.html
Website:
100randomtasks.com
Patreon:
patreaon.com/100randomtasks
Thank you for your support!
Music:
www.bensound.com
This video prepares the CPU for the addition of the stack by altering the design to load the start address of the program from the top 2 bytes of the memory address space.
The circuit is also updated and includes a 2k ROM, 4 line to 16 line decoder to break up the address space into 4k blocks and has the original 8 bit output port as before.
A 2k RAM will be added in the next video for the stack access.
Thanks to everyone who've stuck around for this series! More videos to come. Please subscribe so you don't miss them.
Cheers.
Propeller EEPROM Programmer:
ua-cam.com/video/L7MCQwWsKGw/v-deo.html
Website:
100randomtasks.com
Patreon:
patreaon.com/100randomtasks
Thank you for your support!
Music:
www.bensound.com
Переглядів: 1 325
Відео
EEPROM PROGRAMMER WITH THE PARALLAX PROPELLER!
Переглядів 1,3 тис.2 роки тому
Adding ROM to your homebrew computer requires adding ROM at some point. This short video covers using the Propeller Microcontroller to make an EEPROM programmer. First I outline it's function and go over the code and then build and show the operation of the circuit. Find the link to the code below. If you find what I do here helpful, please consider subscribing. Thank you! Website: www.100rando...
VERILOG MODULES USING CODE ONLY !
Переглядів 6532 роки тому
Instead of using the schematic capture, learn how to connect together multiple verilog modules into a single module. Thanks to everyone who've stuck around for this series! More videos to come. Please subscribe so you don't miss them. Cheers. Website: 100randomtasks.com Patreon: patreaon.com/100randomtasks Thank you for your support! Music: bensound.com
HOW TO CREATE A CPU IN AN FPGA - Part 8 - 16 Bit Address Bus
Переглядів 1,5 тис.2 роки тому
16 BIT ADDRESS BUS The CPU is upgraded for a 16 bit address bus allowing for it to access 64K of memory. The 8 bit program counter and address register are removed and replaced with 16 bit versions as well as 2 new 8 bit registers to generate any 16 bit value. These 4 registers are then connected together to form an address control block that is added to the cpu. Finally, the original program i...
Program your FPGA over Wi-Fi using Xilinx Virtual Cable...Sort Of?
Переглядів 1,6 тис.3 роки тому
This video describes using a Raspberry Pi Pico and an ESP-01 wifi module to create a Xilinx programmer using the Virtual Cable driver. The code is written in micropython and can be downloaded here: www.100randomtasks.com/post/program-your-fpga-over-wi-fi-sort-of The Parallel Programmer can be seen here: www.100randomtasks.com/xilinx-parallel-programmer The micropython image can be found here: w...
HOW TO CREATE A CPU IN AN FPGA - Part 7 - Hello World!
Переглядів 2,5 тис.3 роки тому
Hello World! Finally a working CPU that can manipulate data! First the finishing touches are put on the CPU by adding the control block and tweaking the ALU and address/data bus buffer controls. Then a 2Kx8 ram is added as well as a way to program it along with an output port to display data. A simple assembly program is written and manually programmed and run by the CPU demonstrating it functi...
HOW TO CREATE A CPU IN AN FPGA - Part 6 - Control
Переглядів 2 тис.3 роки тому
In this episode, we cover the heart of the CPU, the control block beginning with going over how instructions are broken down into discrete states that are synchronized by the clock and by combining the current state count with the instruction, the various control lines are activated or deactivated to move data around the CPU to perform the various instruction operations. After creating the cont...
HOW TO CREATE A CPU IN AN FPGA - Part 5 - ALU !
Переглядів 2,4 тис.3 роки тому
In this episode, we cover creating a 4 bit arithmetic logic unit (ALU) with 4 functions; ADD, SUBTRACT, LOGICAL AND, LOGICAL OR. And demonstrate its function using DIP switches and LED's. It also covers the creation of the carry and zero flags. After this, the ALU module is added to the CPU design, changed to 8 bits, and tested with the accumulator using DIP switches and LED's to make sure it i...
HOW TO CREATE A CPU IN AN FPGA - Part 4 - Data Flow
Переглядів 2,6 тис.3 роки тому
In part 4 I go over moving data inside the CPU as well as to and from external memory using a test circuit with DIP switches taking the place of memory. The control lines are brought out of the CPU so that they can be individually controlled. website: www.100randomtasks.com patreon: www.patreon.com/100randomtaks Thank you to all my supporters! music: www.bensound.com
HOW TO CREATE A CPU IN AN FPGA - Part 3 - Multiplexer
Переглядів 3,7 тис.3 роки тому
Part 3 describes, creates, and demonstrates the action of a multiplexer and it's use in the the CPU design. By using a multiplexer, it prevents any possible bus contention ( more than one component driving the bus at any given time) by controlling access to the bus by only one component at a time based on the state of the control lines. Part 1 - Outline and 'Hello World' Test ua-cam.com/video/H...
HOW TO CREATE A CPU IN AN FPGA - Part 2 - Registers
Переглядів 8 тис.3 роки тому
Part II of the series on building a CPU inside a Spartan 3A FPGA. This part demonstrates a 1 bit register with synchronous load and asynchronous reset. Following that it shows the creation of an 8 bit version and the beginnings of the CPU design. In addition, it also has a modified register for the Program Counter which adds an increment line to increment the PC on a clock pulse. Part I can be ...
Build a Low Cost Shop Air Filter
Переглядів 20 тис.3 роки тому
A simple to build air filter for a small shop built in between the ceiling joists using scrap lumber, an unused fan, and a 16x25x1 standard furnace filter. The fan could use more flow and in the future I will replace the existing one for a couple of 110v high flow server fans from the usual Chinese suppliers. Patreon: www.patreon.com/100RandomTasks Thankyou for your support! Website: 100randomt...
Is AliExpress Breadboard PS Worth It?
Переглядів 2034 роки тому
Is an AliExpress breadboard power suppy worth it? Find out as I have a look at a common one available from most China sources. If you aren't comfortable buying from one of the China suppliers, you can grab them from Amazon at this link: www.amazon.com/gp/product/B01LZVRP83/ref=as_li_tl?ie=UTF8&tag=100randomtask-20&camp=1789&creative=9325&linkCode=as2&creativeASIN=B01LZVRP83&linkId=d947b6170e988...
HOW TO CREATE A CPU IN AN FPGA - Part 1
Переглядів 21 тис.4 роки тому
First in a series on creating a custom CPU using Xilinx Spartan 3A FPGA covering cpu outline, verilog file, programming and testing. Link to website: www.100randomtasks.com Link to Parallel Programmer: www.100randomtasks.com/xilinx-parallel-programmer Patreon: www.patreon.com/100RandomTasks Thankyou for your support! It helps me to create more great content. Link to CPU Design pdf: Note: Univer...
bro can you share the verilog file or explain the new IO_buffer you just put it directly, not able to understand how it works
I know this is late, but I am a student going into my 3rd year and really want to get an internship in RTL design or FPGA programming so I am doing some projects. Would this count as a finite state machine? or is it just a bunch of If statements?
I have that same hammer!
why are you using a register for the output here? Is it just personal preference?
17:35
How is this solution holding up ?
Please make more parts
Due to a conflict with a recent Google policy change I am reducing my YT footprint.
This is a plain genious idea diy, No fancy!
to follow through these project, what fpga board do you recommend? I couldn't find that same board that you are using
Can i get a reference for creating my own customized FPGA kit
alu-fast-cache-rom in-memory cpu is the simplest, even multi-core cpu/gpu, same local memory shared multiple access
2x 8-bit = 16-bits, in parallel
an instruction is only a collection of memory pointers (the memory controller takes parameters each cycle directly from L2 shared memory, ie, instruction, memory locations, directly)
simplest logic possible
FP16 rocks
Not with that punny fan
Please continue with this series! I'd love to see the stack and ram added, as well as other features!
Are more parts coming?
Excellent! Thank you!
Any reason you use always @ (*) and registers as opposed to assign statements and a registerless approach in the ALU given that you'll go into a "register base" block afterwards?
Small suggestion... Jump cut more of the FPGA build process.
hi could you make an explanation for the io buf file
If you were to use the Spartan 3A on a custom PCB in place of a 40 pin CPU such as the popular 6502, would the PCB require additional components, or could it just be the FPGA chip?
Hack the ps5 yo~!
Hey buddy may I ask what software do you use to make an fpga schematics.
THIS VIDEO DESEVERS MORE VIEWS
Great idea I like it
Does the same method of setting a carry flag for addition work for unsigned subtraction as well?
Love your channel sir
Thank you so much for this series, you have vastly increased my knowledge in both CPU design/theory and FPGA development. I look forward to more content from this channel.
Yes, bookmarked: fpga cpu
can you imagine intel or AMD's internal development presentations like this today
Just a question. At the end you mentioned that without the constraints it would just assign a random pin, I’ve never seen that happen, in my experience they just don’t connect them to an output. Can you confirm what actually happens, does it assign a random pin or just leave it unconnected?
Thanks for the question. If you have defined i/o pins that are not set using constraints, then the software will place them where it thinks its the best place to put them. If you have an unconnected wire or connection from another block, it will ignore it. You can tell if it is defined by a box around the label at the end of a wire with the direction indicated by the box. Either in, out or in/out on the top level. Hope this helps.
Thanks for this video, but how about OBUFT8?
Basic objects can be used just as easily. Use this link and check out page 132 for the OBUFT. www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/spartan3_hdl.pdf
@@100RandomTasks I'll try tonight, had no idea how to implement that part as my editor is text only =)
who else is working on this project?
Love your videos, thank you so much for sharing your knowledge.
Purchase please...
I'm working on making them available. Stay tuned!
@@100RandomTasks i will...
Too good ! Did u buy the licence for the xilinx ISE or cracked version ?
It's freely available to doenload from Xilinx. You just need to search for it on the site. Cheers.
Hi I am interested in doing this project for my college project so what kind of FPGA board do I need to purchase for making this, also is there any possibility of simulating it on my Laptop Cheers!
lol
I'm working on making this board available but likely won't be ready until the end of January or February.
nice job!
Thanks! Glad you are enjoying it.
where is the description. and is there a download link for the software you use?
Are u coping ben eater video? 😠😠
Thanks for the comment. Ben Eater's vids use discrete ic's to make make his circuits. Im using an fpga. It is a similar format because it lends itself to showing the information in a useful way. And I'm a fan of his channel.
Great video. Liked, subscribed, and looking forward to more.
The benefit of using an FPGA is the almost unlimited control logic decoding, whereas Ben Eater et al used ROMs to decode the controls - an easy solution but often the limiting factor on speed due to the access time of the ROMs. It will be interesting to see how fast you can clock your processor before it fails!
Thanks for the comment. So far the max speed is in the neighbourhood of 60mhz. But the low cost roms look to be about 10mhz. Although I haven't tested this yet.
Can you make a video about the software development tools you use? How to get them, install it and use it? So far it seems to me that getting the right tools is not as straight forward as it seems.
I'll put it on my list for possible future videos. Thanks.
Great tutorial.
Thanks! Glad you liked it.
Thanks man!
I would like a Xilinx board used in this video how could I purchase one?
Currently I'm not selling these but there has been interest so I am planning on pricing it out to see if it's worth doing a small run. Thanks for the interest! Cheers.
Thanks for the try let me know how it goes.
Great project. Please continue make your cpu and yours videos.
Thanks, that is a good and informative review!
Can't belive the algorithm has ysed 11 months to put your channel in my feed. Looks promising. Thanks and please keep banging at it 👍
Thanks. I appreciate it.
This has been out a while 🙂 I can't send a postcard over here for 1$. Getting parts is expensive to. So I could basically order the card just to get the parts.
Spartan board please...