Відео

Hi sir at 1:33:34 the sequence s_add_pipe got failed na sir because after ap1 is asserted in the next clock cycle ap2 to be asserted but in the third case you have shown in after ap1 is asserted ap2 is asserted after 2 clock cycles na sir.Then how we can say that Assertion has passed sir

Great video to start with Assertions.Thank you for Providing such Valuable content sir

Crystal clear concept and a great overview sir

Please make a video on RAL.

Can you please add the source code to review if possible.

Thanks for this video!!

It's an excellent video explaining clocking blocks. It would be great ,if explained with a simulation and wave forms.Thanks for the video

are the tests still available?

is it possbile to share code to review?

first arrange videos in a order .Arrange yopur videos topicwies

I have no experience in dv Passed in 2017 But I want to be as dv Will able to get it

Hi, if the transfer size is 1B for a burst of length 4 and data bus is 4B. What will be the addresses of each transfer? Will it be incremental by 4B or 1B ?

in the video last image "i think" if 2 byte : 1) first byte will be present on 0X8. 2)but second byte uses lower boundary 0x1 bcz only remain one byte is present . please tell me my view is correct or not

Thanks for the explanation in an easy way. i have one confusion, if awsize is 2 then how it is transferring 2 bytes? For 2 bytes transfer awsize also should be 1?

For 0x1ffc, shouldn't the transaction have a ARsize = 1? Same for 0x2000

Informative ..clear explanation without lag🎉😊

🎉🎉

is that tool is free

Informative session ..🎉

Thank you sir for these videos on Assertions, Very well explained. Hopefully many more to come💫

Very well explained sir

Sir, how many days this course will be valid after taking course ?

Thanks

Hi Sir, Since the slave range is till 0x1FFF, how the address of 0x2000 can be initiated ? How the slave would interpret this ?

Very generic ☺

Thanks for covering this topic ! One approach shown in the video is to control the address and WSTR both. Can the same result be achieved by keeping the address the same and only changing the strobes? Eg : The naturally aligned address will be 0x0,0x4,0x8.... ADDR - 0x1000 AWLEN - 0 WSTR 0x1 -> Update the slave memory with byte location 0 (Addr 1000) ADDR - 0x1000 AWLEN - 0 WSTR 0x2-> Update the slave memory with byte location 1 (Addr 1001) ADDR - 0x1000 AWLEN - 0 WSTR 0x4-> Update the slave memory with byte location 2 (Addr 1002) ADDR - 0x1000 AWLEN - 0 WSTR 0x8-> Update the slave memory with byte location 3 (Addr 1003)

Hello Sir. Thanks for the great explanation. I have a doubt here. What is the maximum number of bytes that we can write in one address space? Like you wrote 2 bytes (per beat) of information at the address space 0x1000. So, what is the maximum amount of data that we can write in this address space 0x1000? Thanks in advance!

Pls add examples also

Helpful😊

Can you please constantly upload more videos on testbench development ?

Please do regular videos it will be very helpful

it's time-saving as compared to usual log file analysis, Thanks.

Thanks Anand, please keep sharing more such informative videos

perfect start Anand!!! I'm following this series