Cadence VLSI
Cadence VLSI
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Op-Amp Optimization: Transistor region analysis explained - Op-Amp Part 2
Op-Amp Optimization: Transistor Region Analysis Explained - Opamp Part 2
In this video, we take a deep dive into the operating regions of each transistor within an op-amp design! Learn how to verify if your transistors are in the correct region-cutoff, linear, or saturation-for optimal performance. This step-by-step guide will help you ensure that your op-amp is designed and functioning as efficiently as possible.
Boost your design skills and ensure your op-amp is truly optimized! 💡
We’ll cover:
✅ Why transistor regions matter and how they influence the gain, stability, and accuracy of your op-amp.
✅ Detailed region-by-region analysis for each transistor in the design, giving you insights into your circuit’s strengths and areas for improvement.
✅ Pro tips for checking transistor operating points to make sure your op-amp performs at its best, every time.
Whether you’re just getting started with analog design or looking to fine-tune your understanding of op-amp details, this video will provide valuable insights.
🎬 Be sure to hit Subscribe for more hands-on tutorials, expert tips, and in-depth explorations of electronic design.
Let’s take your skills to the next level together!
Check out our channel here:
www.youtube.com/@CadenceVLSI
CHECK OUT OUR OTHER OPAMP VIDEO
Part 1:- ua-cam.com/video/J5GRwujan3Y/v-deo.html
Переглядів: 282

Відео

Design of Opamp in Cadence Virtuoso and it's AC Gain & Phase Analysis - Op-Amp Part 112:32Design of Opamp in Cadence Virtuoso and it's AC Gain & Phase Analysis - Op-Amp Part 1
Design of Opamp in Cadence Virtuoso and it's AC Gain & Phase Analysis - Op-Amp Part 1
Переглядів 8223 місяці тому
Design of Opamp in Cadence Virtuoso and it's AC Gain & Phase Analysis - Op-Amp Part 1 Ready to level up your circuit design game? In this exclusive tutorial, we’re breaking down the art of designing an operational amplifier in Cadence Virtuoso, with a deep dive into AC Gain vs. Phase analysis! Discover pro techniques to build, analyze, and perfect your Op-Amp for maximum gain and stability. Thi...
Design of SRAM 12T Cell in Cadence Virtuoso and it's DC Analysis #cadence #virtuoso #SRAM6:02Design of SRAM 12T Cell in Cadence Virtuoso and it's DC Analysis #cadence #virtuoso #SRAM
Design of SRAM 12T Cell in Cadence Virtuoso and it's DC Analysis #cadence #virtuoso #SRAM
Переглядів 2 тис.3 місяці тому
🎬 SRAM 12T Design with Cadence Virtuoso! 🎬 Welcome to another video on our channel! In this, we dive deep into the design of an SRAM 12T cell using Cadence Virtuoso, followed by its DC analysis. Whether you're an engineering student, a VLSI enthusiast, or just curious about semiconductor design, this tutorial is tailored for you! 🔧 What You’ll Learn: Step-by-step design process of an SRAM 10T c...
Design of SRAM 10T Cell in Cadence Virtuoso and it's DC Analysis #cadence #virtuoso #SRAM9:17Design of SRAM 10T Cell in Cadence Virtuoso and it's DC Analysis #cadence #virtuoso #SRAM
Design of SRAM 10T Cell in Cadence Virtuoso and it's DC Analysis #cadence #virtuoso #SRAM
Переглядів 2,7 тис.5 місяців тому
🎬 SRAM 10T Design with Cadence Virtuoso! 🎬 Welcome to another video on our channel! In this, we dive deep into the design of an SRAM 10T cell using Cadence Virtuoso, followed by its DC analysis. Whether you're an engineering student, a VLSI enthusiast, or just curious about semiconductor design, this tutorial is tailored for you! 🔧 What You’ll Learn: Step-by-step design process of an SRAM 10T c...
Process Corner Analysis of 7T SRAM in Cadence Virtuoso6:05Process Corner Analysis of 7T SRAM in Cadence Virtuoso
Process Corner Analysis of 7T SRAM in Cadence Virtuoso
Переглядів 6826 місяців тому
#cadence #virtuoso #vlsi #vlsidesign #vlsiprojects #sram #transistors #mtec#mtech #btech #btechprojects #electronics #ece #electronic #testing #phd #c2s #semiconductor #semiconductorphysics #cadence #tcad #modelsim
Design of SRAM 7T Cell in Cadence Virtuoso and SNM Plot #cadence #virtuoso #SRAM5:27Design of SRAM 7T Cell in Cadence Virtuoso and SNM Plot #cadence #virtuoso #SRAM
Design of SRAM 7T Cell in Cadence Virtuoso and SNM Plot #cadence #virtuoso #SRAM
Переглядів 1,1 тис.6 місяців тому
#cadence #virtuoso #vlsi #vlsidesign #vlsiprojects #sram #snm #transistors #mtechprojects #mtech #btech #btechprojects #electronics #ece #electronic #testing #opamp #phd #c2s #semiconductor #semiconductorphysics #cadence #tcad #modelsim
NAND Gate Layout in Cadence Virtuoso8:18NAND Gate Layout in Cadence Virtuoso
NAND Gate Layout in Cadence Virtuoso
Переглядів 7106 місяців тому
#cadence #virtuoso #vlsi #vlsidesign #vlsiprojects #nand #gate #layoutdesign #layout #transistors #mtechprojects #mtech #btechprojects #btech #electronic #electronics #ece #testing #phd #c2s #semiconductor #semiconductorphysics #cadence #tcad #modelsim
Design of SRAM 6T Cell using stacking effect in Cadence Virtuoso6:49Design of SRAM 6T Cell using stacking effect in Cadence Virtuoso
Design of SRAM 6T Cell using stacking effect in Cadence Virtuoso
Переглядів 1,6 тис.7 місяців тому
#cadence #virtuoso #vlsi #vlsidesign #vlsiprojects #sram #transistors #mtechprojects #mtech #btech #btechprojects #electronics #ece #electronic #opamp #testing #phd #c2s #semiconductor #semiconductorphysics #cadence #tools #tcad #modelsim
Design of 3 input AND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign9:34Design of 3 input AND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Design of 3 input AND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Переглядів 9357 місяців тому
#cadence #virtuoso #vlsi #vlsidesign #vlsiprojects #sram #transistors #mtech #mtechprojects #btech #btechprojects #electronic #electronics #ece #opamp #testing #phd #c2s #semiconductor #cadence #tcad #modelsim
CMOS Inverter Layout Design using Cadence Virtuoso | DRC Check17:59CMOS Inverter Layout Design using Cadence Virtuoso | DRC Check
CMOS Inverter Layout Design using Cadence Virtuoso | DRC Check
Переглядів 4318 місяців тому
#cadence #virtuoso #vlsi #vlsidesign #vlsiprojects #vlsitraining #layout #inverter #transistors #mtechprojects #mtech #btechprojects #btech #electronic #electronics #ece #opamp #testing #phd #c2s #semiconductor #semiconductorphysics #cadence #tcad #modelsim
NMOS Id vs Vgs Characteristic using Cadence Virtuoso | Power Consumption5:00NMOS Id vs Vgs Characteristic using Cadence Virtuoso | Power Consumption
NMOS Id vs Vgs Characteristic using Cadence Virtuoso | Power Consumption
Переглядів 2319 місяців тому
#cadence #virtuoso #vlsi #vlsidesign #c2s #modelsim #phd #semiconductor #semiconductorphysics #tcad #mtech #mtechprojects #btech #btechprojects #electronics #electronic #ece #nmos #pmos #transistors
NMOS Id vs Vds Characteristics using Cadence Virtuoso6:15NMOS Id vs Vds Characteristics using Cadence Virtuoso
NMOS Id vs Vds Characteristics using Cadence Virtuoso
Переглядів 8659 місяців тому
#cadence #virtuoso #vlsi #vlsidesign #vlsiprojects #nmos #transistors #mtechprojects #mtech #btech #btechprojects #electronics #ece #phd #c2s #semiconductor #semiconductorphysics #edatool #tcad #modelsim
DC Analysis and Power Dissipation of SRAM 6T Cell in Cadence Virtuoso3:35DC Analysis and Power Dissipation of SRAM 6T Cell in Cadence Virtuoso
DC Analysis and Power Dissipation of SRAM 6T Cell in Cadence Virtuoso
Переглядів 2,2 тис.9 місяців тому
DC Analysis and Power Dissipation of SRAM 6T Cell in Cadence Virtuoso
Design of SRAM 6T Cell in Cadence Virtuoso and it's DC Analysis #cadence #virtuoso #SRAM11:39Design of SRAM 6T Cell in Cadence Virtuoso and it's DC Analysis #cadence #virtuoso #SRAM
Design of SRAM 6T Cell in Cadence Virtuoso and it's DC Analysis #cadence #virtuoso #SRAM
Переглядів 8 тис.9 місяців тому
Design of SRAM 6T Cell in Cadence Virtuoso and it's DC Analysis #cadence #virtuoso #SRAM
Design of Half Adder Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign4:43Design of Half Adder Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Design of Half Adder Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Переглядів 7829 місяців тому
Design of Half Adder Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Symbol Creation of XOR Gate in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign #virtuoso4:19Symbol Creation of XOR Gate in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign #virtuoso
Symbol Creation of XOR Gate in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign #virtuoso
Переглядів 84910 місяців тому
Symbol Creation of XOR Gate in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign #virtuoso
Design of XOR Gate Schematic in Cadence Virtuoso9:05Design of XOR Gate Schematic in Cadence Virtuoso
Design of XOR Gate Schematic in Cadence Virtuoso
Переглядів 6 тис.10 місяців тому
Design of XOR Gate Schematic in Cadence Virtuoso
Design of 2×1 Multiplexer using transmission gate logic in Cadence Virtuoso #cadence #virtuoso #vlsi13:42Design of 2×1 Multiplexer using transmission gate logic in Cadence Virtuoso #cadence #virtuoso #vlsi
Design of 2×1 Multiplexer using transmission gate logic in Cadence Virtuoso #cadence #virtuoso #vlsi
Переглядів 2,7 тис.11 місяців тому
Design of 2×1 Multiplexer using transmission gate logic in Cadence Virtuoso #cadence #virtuoso #vlsi
Design of NOR Gate Schematic in Cadence Virtuoso #virtuoso #cadence #vlsi #vlsidesign7:59Design of NOR Gate Schematic in Cadence Virtuoso #virtuoso #cadence #vlsi #vlsidesign
Design of NOR Gate Schematic in Cadence Virtuoso #virtuoso #cadence #vlsi #vlsidesign
Переглядів 460Рік тому
Design of NOR Gate Schematic in Cadence Virtuoso #virtuoso #cadence #vlsi #vlsidesign
Design of OR Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign7:28Design of OR Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Design of OR Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Переглядів 1,7 тис.Рік тому
Design of OR Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Design of NAND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign8:24Design of NAND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Design of NAND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Переглядів 464Рік тому
Design of NAND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Design of AND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign11:01Design of AND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Design of AND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Переглядів 4,6 тис.Рік тому
Design of AND Gate Schematic in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Inverter using Stimuli #cadence #virtuoso #vlsi #vlsidesign5:53Inverter using Stimuli #cadence #virtuoso #vlsi #vlsidesign
Inverter using Stimuli #cadence #virtuoso #vlsi #vlsidesign
Переглядів 180Рік тому
Inverter using Stimuli #cadence #virtuoso #vlsi #vlsidesign
Inverter design in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign16:31Inverter design in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Inverter design in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign
Переглядів 558Рік тому
Inverter design in Cadence Virtuoso #cadence #virtuoso #vlsi #vlsidesign

КОМЕНТАРІ

  • @lucusjourney2058
    @lucusjourney2058 14 годин тому

    why my output is like mountains? please reply

  • @kishorpatil6562
    @kishorpatil6562 14 днів тому

    Hlo will u pls upload layout of 6t sram

  • @ABHIMANYUSHARMA-ir7tj
    @ABHIMANYUSHARMA-ir7tj 20 днів тому

    mam please make a video on decoder from Cmos transmission gate

  • @DevRaj-xd3mf
    @DevRaj-xd3mf 26 днів тому

    How did u make the inverter only two pins how to remove vdd and gnd

    • @CadenceVLSI
      @CadenceVLSI 21 день тому

      Provide the VDD and VSS inputs in the schematic of inverter, and then create the symbol. This way, you don't need separate pins for VDD and VSS.

  • @BenjaminHsu-kb3ks
    @BenjaminHsu-kb3ks 26 днів тому

    Ma’am thank you so much for sharing this knowledge btw is there any DRAM tutorial on virtuoso

    • @CadenceVLSI
      @CadenceVLSI 21 день тому

      Not yet, but I'll upload it soon

  • @ABHIMANYUSHARMA-ir7tj
    @ABHIMANYUSHARMA-ir7tj Місяць тому

    thank you very much mam 🥰🥰🥰🥰🥰🥰🥰🥰 please teach us like that and mam please upload some videos on analog design

  • @chandansp901
    @chandansp901 Місяць тому

    How did you change that current dource to resistor

  • @kshitij9106
    @kshitij9106 Місяць тому

    can you pls give some idea about the read operation, i'll pay for it if u want

  • @salmanakhter2225
    @salmanakhter2225 2 місяці тому

    Mam I follwed all the steps correctly but my graph is not show butterfly graph.please hele ma'am

  • @dinhhoang-o1i
    @dinhhoang-o1i 3 місяці тому

    Could you make a video about drawing the Write Static Noise Margin (WSNM) for SRAM? I've researched thoroughly but couldn't find a way to draw it.

  • @dinhhoang-o1i
    @dinhhoang-o1i 3 місяці тому

    Could you make a video about drawing the Write Static Noise Margin (WSNM) for SRAM? I've researched thoroughly but couldn't find a way to draw it.

  • @manandaderwal1378
    @manandaderwal1378 3 місяці тому

    Ma'am i am not getting the butterfly curve with same circuit I am using gpdk90. CAN YOU PLEASE HELP ME !!

    • @CadenceVLSI
      @CadenceVLSI 3 місяці тому

      Feel free to ask your questions or doubts here.

    • @anishkumarmondal4199
      @anishkumarmondal4199 2 місяці тому

      @manandadrewal1378 you got it correct?

  • @saiprajothmallyala7955
    @saiprajothmallyala7955 3 місяці тому

    maam can you do it on TINA software as well pls

  • @AKASHKUMAR-t2c1p
    @AKASHKUMAR-t2c1p 3 місяці тому

    thanks a lot mam this video is so unique please upload more video i want ... play list cadence virtuoso 13T analysis. i am working in my thesis "Readiation Hardened in sram"

  • @SAbrooadcom
    @SAbrooadcom 3 місяці тому

    Thank you

  • @opshot1144
    @opshot1144 4 місяці тому

    mam plz tell for 11Transistors mam

  • @SAbrooadcom
    @SAbrooadcom 4 місяці тому

    👍

  • @archanaanand8797
    @archanaanand8797 4 місяці тому

    Thank you so much. This helped me a lot❤

  • @suchithareddy953
    @suchithareddy953 4 місяці тому

    Mam can you provide your email.address. actually i am working on sram. I have some doubts . Can you please share your email address

    • @CadenceVLSI
      @CadenceVLSI 3 місяці тому

      Feel free to ask your questions or doubts in the comments section.

  • @suchithareddy953
    @suchithareddy953 4 місяці тому

    Hello mam. Can you do a vedio how to design a radiation hardened sram

  • @suchithareddy953
    @suchithareddy953 4 місяці тому

    Hello mam

  • @Straight_Forward615
    @Straight_Forward615 4 місяці тому

    Thank you so much ma'am. Your videos are helping me a lot.

  • @SAbrooadcom
    @SAbrooadcom 4 місяці тому

    Thank you

  • @academicstuff548
    @academicstuff548 4 місяці тому

    Fantastic explanation.

  • @dinhhoang-o1i
    @dinhhoang-o1i 5 місяців тому

    why did you add VDC=1v at point Q.when BL line is already powered.i really need explanation

    • @CadenceVLSI
      @CadenceVLSI 3 місяці тому

      This serves several purposes: It will help to maintain a stable voltage level at the node as SRAM cells need stable reference points to prevent unwanted flipping of stored values due to noise or fluctuations. Sometimes, a precharge voltage is applied to initialize the cell to a specific state before performing read or write operations. Adding a fixed voltage source at specific nodes can help analyze the cell's static characteristics, such as noise margin and stability.

  • @dinhhoang-o1i
    @dinhhoang-o1i 5 місяців тому

    why did you add VDC=1v at point Q.when BL line is already powered.i really need explanation

    • @CadenceVLSI
      @CadenceVLSI 3 місяці тому

      This serves several purposes: It will help to maintain a stable voltage level at the node as SRAM cells need stable reference points to prevent unwanted flipping of stored values due to noise or fluctuations. Sometimes, a precharge voltage is applied to initialize the cell to a specific state before performing read or write operations. Adding a fixed voltage source at specific nodes can help analyze the cell's static characteristics, such as noise margin and stability.

  • @AbhimanyuSharma-e6q
    @AbhimanyuSharma-e6q 5 місяців тому

    Thank you very much mam🥰🥰🥰🥰🥰🥰 please teach about vlsi concepts of mosfets and help us to design some digital circuits

  • @kusumapasupuleti7496
    @kusumapasupuleti7496 5 місяців тому

    Can u upload 10t sram transient analysis

  • @LaLa-x3y
    @LaLa-x3y 5 місяців тому

    Can i calculate the SNM after getting the butterfly curves, ma'am? Thank you

    • @CadenceVLSI
      @CadenceVLSI 3 місяці тому

      Yes, you can calculate the SNM after obtaining the butterfly curves.

  • @hainguyenthanh8375
    @hainguyenthanh8375 5 місяців тому

    I looking forward to video related Ip, memory, such as: DDRAM, DDRAM1,2,3,... 🤗

  • @mr.vardhan8632
    @mr.vardhan8632 5 місяців тому

    Please upload video on 12t sram

    • @CadenceVLSI
      @CadenceVLSI 3 місяці тому

      ua-cam.com/video/0rWzlU9np7U/v-deo.htmlsi=pqb8fNjQJ2fkH8Wz

  • @ch.yaminic1361
    @ch.yaminic1361 5 місяців тому

    Maam please do a video on 12 t sram

    • @CadenceVLSI
      @CadenceVLSI 3 місяці тому

      ua-cam.com/video/0rWzlU9np7U/v-deo.htmlsi=pqb8fNjQJ2fkH8Wz

  • @CHINTADAMADHUSUDHANARAO
    @CHINTADAMADHUSUDHANARAO 5 місяців тому

    Maam please do a video on 12t sram

    • @CadenceVLSI
      @CadenceVLSI 3 місяці тому

      ua-cam.com/video/0rWzlU9np7U/v-deo.htmlsi=pqb8fNjQJ2fkH8Wz

  • @Sunny_9048
    @Sunny_9048 6 місяців тому

    Mam can you explain Design of low power SRAM using 10Transiator

    • @CadenceVLSI
      @CadenceVLSI 5 місяців тому

      ua-cam.com/video/g0fJjbj_OnE/v-deo.html

  • @Sunny_9048
    @Sunny_9048 6 місяців тому

    Mam is cadence software Is free

  • @hainguyenthanh8375
    @hainguyenthanh8375 6 місяців тому

    How to identify technology 90nm and 180nm Using cadance ?

    • @CadenceVLSI
      @CadenceVLSI 5 місяців тому

      When you started making the library, you must have chosen the technology you wanted to use. And incase you want to check the technology later, follow these steps: 1. Go to 'Tools → Library Manager' in Virtuoso. 2. Find the library you're working with, right-click on it, and select 'Properties.' 3. You'll see the Technology Library name, which indicates the technology node (e.g., 90nm or 180nm).

    • @hainguyenthanh8375
      @hainguyenthanh8375 5 місяців тому

      @@CadenceVLSI thanks your answer

  • @kajalkhairnar809
    @kajalkhairnar809 6 місяців тому

    Keep it up👍🏻

  • @SANJAYYADAV-jp2dt
    @SANJAYYADAV-jp2dt 6 місяців тому

    good

  • @ShubhamYadav-zj4st
    @ShubhamYadav-zj4st 6 місяців тому

    Good going 👍

  • @whathehellooo
    @whathehellooo 6 місяців тому

    can u do 10T SRAM (TRIO)

    • @CadenceVLSI
      @CadenceVLSI 5 місяців тому

      ua-cam.com/video/g0fJjbj_OnE/v-deo.html

  • @vinayakulkarni5336
    @vinayakulkarni5336 6 місяців тому

    Thank you so much mam for this video 😊

  • @SANJAYYADAV-jp2dt
    @SANJAYYADAV-jp2dt 6 місяців тому

    Simplyfied and understandable

  • @karanchoudhary5652
    @karanchoudhary5652 6 місяців тому

    Why their is a spike in the output waveform

    • @CadenceVLSI
      @CadenceVLSI 6 місяців тому

      When both the inputs are 1 we generally see these spikes, this happens when the inputs are not perfectly synchronised and when there is a slight delay in one input.

  • @vinayakulkarni5336
    @vinayakulkarni5336 6 місяців тому

    mam iska 7T SRAM CELL ka video mil sakta hai kya ?

    • @CadenceVLSI
      @CadenceVLSI 6 місяців тому

      ua-cam.com/video/D1tALj2mC2k/v-deo.html

  • @RIYAYADAV-i6f4m
    @RIYAYADAV-i6f4m 7 місяців тому

    Well explained ma'am Thankyou

  • @the.businesspreneur
    @the.businesspreneur 7 місяців тому

    Pls make a vdeo on its layout too...

    • @CadenceVLSI
      @CadenceVLSI 6 місяців тому

      watch this for basic ua-cam.com/video/_X7016gtAFs/v-deo.html

  • @mrahil1333
    @mrahil1333 8 місяців тому

    Hi this layout is not good poly cannot be bent

    • @CadenceVLSI
      @CadenceVLSI 8 місяців тому

      It's not that you can't bend it-you can. However, you need to ensure it doesn't overlap with other poly. This is just an explanation for designing the layout; if you can create a more accurate design, that would be even better.

  • @RoshanKumar-vf4tt
    @RoshanKumar-vf4tt 8 місяців тому

    Mam can you make video on 3 input AND gate?

    • @CadenceVLSI
      @CadenceVLSI 8 місяців тому

      ua-cam.com/video/aKcnyKXdoDo/v-deo.html

  • @pratikmohanty1498
    @pratikmohanty1498 8 місяців тому

    How you designed the invertersymbol???

    • @CadenceVLSI
      @CadenceVLSI 8 місяців тому

      I've already designed that in my previous video ua-cam.com/video/oCAus4A1sSg/v-deo.html

  • @tamphuc6159
    @tamphuc6159 8 місяців тому

    Please give me the link to download cadence virtuoso