Відео

46680 Towne Drive

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Wow... Spelled FPGAs wrong im not gonna trust this

So many details in the slides. It's easy to get lost

I'd love the presentation material as well. Great session!

Is there any chance for me to get the presentation material? :)

How can be the credits exchange mechanism work without LLCRD flit in CXL 3.0? I mean which flit should carry credit information after INIT.Pram Flit being sent.

Will these Micron memory expansion cards be available for Workstations platforms as well, like the Threadripper and Threadripper Pro? Or will there only be support for the Epic 9004 series? If there will be workstation support, are there plans for these cards being available as PCIe5 x16 slot variant add-in boards? With Intel Optane gone, I really hope CXL and Micron will include support for Workstation users as well.

Promo-SM

and the gpu processor, can control a cxl port, how caché memory?

I'm trying to learn what problem CXL is designed to solve? How is this any different than standard system memory?

why blur the text, it's pretty much obvious this is a 96-thread × 2 cpu system.

how do i install cxl to help reduce Texture Memory usage in RAM ?

Why do you think the CXL devices' cache size should be around 1MB? I'm curious about this because there are many GPUs that have a cache larger than 1MB

Can I have a pdf of this video please since your explanation is very I want to go through this

Will it go point to point over chassis

I wonder if CXL 2.0 would be able to be used to create a virtual machine that runs a single kernel that runs on all hardware as though it were one giant system. Not that I can think of a use case for this, it is just fascinating.

I wonder when the CXL 3.0 Drafts would be allowed to be previewed by the public :/

The graphic in the beginning misspells "FPGA".

Very informative!

Thanks for the great video. I have a few questions about the video. In the case of Multiple Logical Device (MLD), one CXL Memory Node is likely to consist of 1 ~ 4 channels. Is the host assigned to each channel? Or, if this memory node is E3.S form factor, there will be 20 or 40 DRAM packages, are the hosts allocated in units of packages?

Does a CXL Device support hotplug?

How about the memory latency behind the CXL?

It seems the fabric manager manages system memory for all those hosts. In this case, the fabric manager has higher exception level than hypervisors. What exactly is this piece of SW?

Buy NLST = NLST = CXL = Winner

Which version of ubuntu is this which understands CXL ?

Very informative

Thanks a lot for the presentation. It clarifies many of my questions.

main question - what is the speed?

Excellent presentation, Rick