Debarshi Chatterjee
Debarshi Chatterjee
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Implement randc using rand in SV (Design Verification interview question for FAANG)
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Відео

N Queen using System Verilog Constraints (DV Interview question - Apple/Google etc)N Queen using System Verilog Constraints (DV Interview question - Apple/Google etc)
N Queen using System Verilog Constraints (DV Interview question - Apple/Google etc)
Переглядів 7127 місяців тому
Sudoku (using System Verilog Constraint) - Interview Question for Apple/Google etcSudoku (using System Verilog Constraint) - Interview Question for Apple/Google etc
Sudoku (using System Verilog Constraint) - Interview Question for Apple/Google etc
Переглядів 4,8 тис.Рік тому
System Verilog Constraint Interview Question
GraphCov: RTL Graph Based Test Biasing for Exploring Uncharted Coverage Landscape.pdfGraphCov: RTL Graph Based Test Biasing for Exploring Uncharted Coverage Landscape.pdf
GraphCov: RTL Graph Based Test Biasing for Exploring Uncharted Coverage Landscape.pdf
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Automated Coverage Closure
FIFO Topology Aware Stalling for Accelerating Coverage ConvergenceFIFO Topology Aware Stalling for Accelerating Coverage Convergence
FIFO Topology Aware Stalling for Accelerating Coverage Convergence
Переглядів 902 роки тому
Systematic Constraint Relaxation (SCR): Hunting for Over-Constrained StimulusSystematic Constraint Relaxation (SCR): Hunting for Over-Constrained Stimulus
Systematic Constraint Relaxation (SCR): Hunting for Over-Constrained Stimulus
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A heuristic for automatically identifying over-constraints in a System Verilog test bench
BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem, DVCON 2022BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem, DVCON 2022
BatchSolve: A Divide and Conquer Approach to Solving the Memory Ordering Problem, DVCON 2022
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An approach to easily verify memory ordering rules at integration level Test Benches without the high overhead of transaction tracking
Deep Stalling using a Coverage Driven Genetic Algorithm FrameworkDeep Stalling using a Coverage Driven Genetic Algorithm Framework
Deep Stalling using a Coverage Driven Genetic Algorithm Framework
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Application of Deep Learning to FIFO Stalling
Solving NxN Tic-Tac-Toe using System Verilog Constraints (Interview Question!)Solving NxN Tic-Tac-Toe using System Verilog Constraints (Interview Question!)
Solving NxN Tic-Tac-Toe using System Verilog Constraints (Interview Question!)
Переглядів 3,1 тис.3 роки тому
This is a generalization of the 3x3 tic-tac-toe problem. Providing a SV constraint based solution for the general case. Code: drive.google.com/file/d/1nGD8VffIPE_GktUOVO4hmrqfUjOh-aBi/view?usp=sharing
FIFO VC Dependency Graph and Its Application to System Level Deadlock Verification #DVCON_US 2021FIFO VC Dependency Graph and Its Application to System Level Deadlock Verification #DVCON_US 2021
FIFO VC Dependency Graph and Its Application to System Level Deadlock Verification #DVCON_US 2021
Переглядів 3273 роки тому
Presenting a graph-based hardware deadlock detection technique that can be applied at unit, integration as well as system level. Paper (PDF): drive.google.com/file/d/10cMDUmG6SQetDEOSnKE71RYW0rv5d5i3/view?usp=sharing Slides (PDF): drive.google.com/file/d/1Cz1SM5jHmbnHaV0XJpdq3Ma7kaRrceEF/view?usp=sharing