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VHDL 101: VHDL Circuit Design Part 1: Fundamentals and Methodologies

VHDL 101 | VHDL Circuit Design Part 2: Advanced Concepts and Behavioral Modeling

VHDL 101 | VHDL Circuit Simulation Part 1: Behavior Modeling, Timing, and File I/O

VHDL 101 - VHDL Circuit Simulation Part 2: Stimulus Generation and Behavior Verification

FPGA 101: FPGA Circuit Design I: Synchronous and Asynchronous Design Techniques

FPGA 101: FPGA Circuit Design II: Interfaces and Best Practices

Using the Adaptive SoC TRDs to Test Custom Image Recognition Tasks

We will explore the fastest way to validate early concepts and tests for performance of challenging processing tasks on various of AMD’s FPGA-based device families. The readily available reference designs for the families of Zynq Ultrascale+ MPSoC and Versal Adaptive SoCs can be deployed as a platform to focus on the actual design challenges you need to solve without bothering to create a full system first place.
The webinar will walk through this approach with focus on the tool flow and operation of the respective designs.
Would you like to know more about this topic?
plc2.com/training/easy-start-embedded-for-zynq-ultrascale-mpsoc-systems_es/
plc2.com/training/compact-versal-adaptive-soc-for-the-software-designer_wo/
plc2.com/training/compact-zynq-ultrascale-mpsoc-for-the-hardware-designer_wo/
Check out our training overview:
plc2.com/training/
Download our interactive training calendar:
plc2.com/wp-content/uploads/2024/10/PLC2_Training_Calendar_2025.pdf
Connect with PLC2 on social media:
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Переглядів: 24

Відео

VHDL 101: VHDL Circuit Design Part 1: Fundamentals and Methodologies

VHDL 101: VHDL Circuit Design Part 1: Fundamentals and Methodologies

VHDL 101: VHDL Circuit Design Part 1: Fundamentals and Methodologies

Переглядів 3519 годин тому

Welcome to the first installment of our comprehensive webinar series on VHDL circuit design. In this session, we will delve into fundamental concepts and methodologies crucial for designing FPGAs using VHDL. We will explore the VHDL design flow, language concepts, and practical applications through examples. Would you like to know more about this topic? plc2.com/training/easy-start-fpga-vivado_...

VHDL 101 | VHDL Circuit Design Part 2: Advanced Concepts and Behavioral Modeling

VHDL 101 | VHDL Circuit Design Part 2: Advanced Concepts and Behavioral Modeling

VHDL 101 | VHDL Circuit Design Part 2: Advanced Concepts and Behavioral Modeling

Переглядів 1819 годин тому

Welcome to the second part of our comprehensive webinar series on VHDL circuit design. In this session, we will delve deeper into VHDL's advanced concepts, focusing on designing with VHDL, behavioral modeling, and verification techniques. Would you like to know more about this topic? plc2.com/training/easy-start-fpga-vivado_es/ plc2.com/training/compact-vhdl-for-simulation_ol/ plc2.com/training...

VHDL 101 | VHDL Circuit Simulation Part 1: Behavior Modeling, Timing, and File I/O

VHDL 101 | VHDL Circuit Simulation Part 1: Behavior Modeling, Timing, and File I/O

VHDL 101 | VHDL Circuit Simulation Part 1: Behavior Modeling, Timing, and File I/O

Переглядів 10119 годин тому

Welcome to the first part of our webinar series on VHDL circuit simulation. This session focuses on essential aspects of behavior modeling, timing simulation, and file Input/Output (I/O) using VHDL. Join us to explore these critical concepts and their practical applications through real-world examples. Would you like to know more about this topic? plc2.com/training/easy-start-fpga-vivado_es/ pl...

VHDL 101 - VHDL Circuit Simulation Part 2: Stimulus Generation and Behavior Verification

VHDL 101 - VHDL Circuit Simulation Part 2: Stimulus Generation and Behavior Verification

VHDL 101 - VHDL Circuit Simulation Part 2: Stimulus Generation and Behavior Verification

Переглядів 1419 годин тому

Welcome to the second part of our webinar series on VHDL circuit simulation. In this session, we will focus on generating diverse stimuli for simulation purposes and verifying behavior within the simulated environment. Join us to explore advanced stimulus generation techniques and behavior checking in VHDL simulations through practical examples. Would you like to know more about this topic? plc...

FPGA 101: FPGA Circuit Design I: Synchronous and Asynchronous Design Techniques

FPGA 101: FPGA Circuit Design I: Synchronous and Asynchronous Design Techniques

FPGA 101: FPGA Circuit Design I: Synchronous and Asynchronous Design Techniques

Переглядів 26День тому

In this session of our FPGA 101 basic webinar series, we will dive deep into the foundational concepts of synchronous versus asynchronous design techniques. We will explore RAMs, FIFOs, and the art of designing state machines in the context of AMD FPGA development. Would you like to know more about this topic? plc2.com/training/compact-fpga-circuit-design-technique_wo/ plc2.com/training/profess...

FPGA 101: FPGA Circuit Design II: Interfaces and Best Practices

FPGA 101: FPGA Circuit Design II: Interfaces and Best Practices

FPGA 101: FPGA Circuit Design II: Interfaces and Best Practices

Переглядів 68День тому

This webinar will focus on FPGA interface design and understanding essential rules and best practices. We will explore advanced interface design concepts and highlight best practices in AMD FPGA development with practical examples. Would you like to know more about this topic? plc2.com/training/compact-fpga-circuit-design-technique_wo/ plc2.com/training/professional-fpga-circuit-design-techniqu...

FPGA 101: Mastering Clock Domain Crossing: Strategies for Synchronization and Stability

FPGA 101: Mastering Clock Domain Crossing: Strategies for Synchronization and Stability

FPGA 101: Mastering Clock Domain Crossing: Strategies for Synchronization and Stability

Переглядів 42День тому

In this episode of the 101 webinar series, our expert explores synchronous and asynchronous systems, focusing on topics such as interfacing domains with different clock frequencies and the insertion of Clock Domain Crossing circuits to handle flip-flop metastability in FPGA design. Would you like to know more about this topic? plc2.com/training/compact-fpga-circuit-design-technique_wo/ plc2.com...

FPGA 101: FPGA Timing Constraints: A Comprehensive Overview

FPGA 101: FPGA Timing Constraints: A Comprehensive Overview

FPGA 101: FPGA Timing Constraints: A Comprehensive Overview

Переглядів 17День тому

Our experts address the necessity of timing constraints in FPGA design to ensure, that a circuit meets its specific performance goals using parameters, such as a clock period. Furthermore, the needed framework for timing constraint specification is explained. Would you like to know more about this topic? plc2.com/training/compact-timing-constraints-and-analysis_wo/ plc2.com/training/compact-tim...