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Ken's Interview Questions
United States
Приєднався 18 лис 2020
A place where hardware engineers, both digital design or verification, can practice commonly asked interview questions.
System Verilog Interview Question: Data Types Interview Questions Part 1
#UVM #Systemverilog #verilog #interviewquestions #hardwareengineering #coding #electronicsengineering #datatype #integers #realnumbers #questionsandanswers
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Відео
System Verilog Interview Question: Write SV function to swap two variables
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System Verilog Interview Question: Write SV function to swap two variables #UVM #Systemverilog #verilog #interviewquestions #hardwareengineering #coding #electronicsengineering
System Verilog Interview Question: Write a task to generate a clock with the given frequency in MHz?
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System Verilog Interview Questions: Write an SV task to generate a clock with the given frequency in MHz? FYI for this example to work duty ratio can only be 0.5
System Verilog Interview Question: What is the difference between a Verilog/SV Task and Function?
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System Verilog Interview Question: What is the difference between a Verilog/SV Task and Function?
What is UVM Reporting or Message Mechanism ? UVM Verbosity Part 4?
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UVM Interview Question: What is UVM Reporting or Message Mechanism ? Part 4. Verbosity
System Verilog Interview Question: Write the code for D-Flip Flop in System Verilog?
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System Verilog Interview Question: Write the code for D-Flip Flop in System Verilog?
What is UVM Reporting or Message? Part 3 UVM Actions?
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UVM Interview Question: What is UVM Reporting or Message Mechanism ? Part 3. Actions,
UVM Report/Message Introduction & Functions Part 2 (Severity, Actions, Verbosity)
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UVM Report/Message Introduction & Functions Part 2 (Severity, Actions, Verbosity) Part 2 deals with Severity
UVM Report/Message Introduction & Functions (Severity, Actions, Verbosity)
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UVM Interview Questions What is UVM Reporting or Message Mechanism? Part 1. UVM Report/Message Introduction & Functions, Part 2. Severity, Part 3. Actions, Part 4. Verbosity
UVM Questions: What happens in the “build phase”? Why is the build phase top-down?
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UVM Interview Questions: What happens in the “build phase”? Why is the build phase top-down? Explain the “build phase” of a UVM component?
UVM Question: What happens in the “end of elaboration phase”?
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UVM Interview Question: What happens in the “end of elaboration phase”? Explain the “end of elaboration phase” of a UVM component?
UVM Question: What happens in the run phase of a UVM component? Is run phase top-down or bottom-up?
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What happens in the run phase of a UVM component? Is UVM run phase top-down or bottom-up?
UVM Questions: Can you describe different phases and sub-phases of a UVM component?
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List out all the phases and sub-phases of a UVM component? Can you describe different phases of a UVM component?
UVM Questions: What are the benefits of UVM? Is it independent from System Verilog?
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UVM Questions: What are the benefits of UVM? Is it independent from System Verilog?
What is a virtual sequencer/sequence? What is the difference between a virtual sequencer/sequence?
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What is a virtual sequencer/sequence? What is the difference between a virtual sequencer/sequence?
UVM Question: What is the difference between UVM transaction and UVM sequence item?
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UVM Question: What is the difference between UVM transaction and UVM sequence item?
How and why is configuration database (config_db) used? What are the set and get functions?
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How and why is configuration database (config_db) used? What are the set and get functions?
UVM Question: What is a UVM config db ?
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UVM Question: What is a UVM config db ?
UVM Ques: Describe the handshake between uvm_sequence, uvm_sequencer, uvm_driver and interface/DUT?
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UVM Ques: Describe the handshake between uvm_sequence, uvm_sequencer, uvm_driver and interface/DUT?
UVM Interview Questions: What is early randomization and late randomization in a UVM environment?
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UVM Interview Questions: What is early randomization and late randomization in a UVM environment?
What is a UVM sequence (uvm_sequence) ? UVM sequence coding example.
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What is a UVM sequence (uvm_sequence) ? UVM sequence coding example.
UVM Interview Questions What is UVM factory? What is factory override and override types?
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UVM Interview Questions What is UVM factory? What is factory override and override types?
UVM Questions: What is the difference between UVM create and new() , UVM object and component?
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UVM Questions: What is the difference between UVM create and new() , UVM object and component?
UVM Questions: What is p_sequencer or m_sequencer?
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UVM Questions: What is p_sequencer or m_sequencer?
Channel Introduction: Hardware Engineering Interview Questions
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Channel Introduction: Hardware Engineering Interview Questions
Cicero Rapids
Nathan Junction
Doyle Alley
Thank you! Very clear to me.
sir can factory also be consider as a global data base?
Thanks, it is very useful!
Stehr Bypass
Could you also solve problems on umm?, more practical examples?
what is my_seq_item?
How does the driver handles if the DUT is giving more then one or out of order responses back, how the driver send same response back to original sequence and not any other sequence?
Hi ken If there is no config db in system verilog and we don’t set or get virtual interface there what would we do there and what is advantage here please explain
Use non blocking. a<=b; b<=a;
Use non blocking. a<=b; b<=a;
Kenneth Sean "Ken" Carson Jr. is a fashion doll introduced by American toy company Mattel in 1961 as the counterpart of Barbie, who had been introduced two years earlier.
Can’t we directly use array sort method and return array[1]? Which will basically be second smallest after sorting
yes we can but complexity would be nlogn where this solution is O(n)
Hi, But as per LRM function can have outputs.
Driver needs run_phase()
Why not to use #(1ps*half_period_in_ps) clk = ~clk;
Have you seen successful use of the sub phases? Is that normal to define subphases along with run_phase?
What was the idea behind having sequencer? In most cases it looks like an extra layer without good purpose. Most of sequencers implementations I saw were plain proxy between sequencer and driver. Sequencer layer weren't doing any work. I would say it only make sense if you actually have an arbitration based on priority or you have to control sequencer e.g. by purging FIFO when reset or end of the test comes.
there are multiple reasons, the first as you mentioned providing a arbitration for sequence request and grand. second, sequencer provide a hierarchical component for sequence, if you wanna pass some config setting, sequence can retrieve the seqr handler to config your transaction in running time. Then if you are trying to implement some complicate sequence like layer sequences, sequencer offer a convenient way to implement that.
@@kuangquan08 1. what do you mean by layer sequences? 2. I don't see why configuration idea is good unless that is runtime driver specific configuration (there are better uvm ways, imo for other configurations). Then, again, why don't use driver for that type of configuration? I believe arbitration argument is good other arguments not so much convincing.
Good!! Tks
Everywhere it is mentioned that UVM sequence is a collection of sequence items.So suppose I have 2 sequence items ,one for write , one for read..does this mean a single sequence can have both the sequence items..in all examples there s one sequence for one sequence items..then how is sequence a collection of sequence items??
Promo'SM
Hi, Default values of smallest and second_smallest will be 0. So, this function will return only 0. (assuming the array has + numbers)
Integer have four state?
yes "integer" data type has 4 states, where as "int" has 2 states.
Is it possible to set config db in lower hierarchy and get it in upper hierarchy?
Yes, it is possible to set the config db in a lower level and obtain it in a higher hierarchy. One way to prevent issues is to do config db set in an earlier phase in the lower level hierarchy and get it from config db in later phase.
Thanks for a great video.
Glad you liked it!
does ovm have late randomisation
Yes, similar to UVM.
I hope you come back to make more of these videos Ken. They were very helpful in my interview prep. Thank you
More to come! :)
Nice video
Thanks
Thank you, very useful
Glad it was helpful!
Hi Ken. I have few queries, 1)What is the argument passed in item done function? 2) when we use item_done () with and without argument in our environment?
Hi Naseem, 1) Item done take a ref of the sequence item that has finished running. 2) Item done is typically called without an argument, when you call it from within the sequence item itself and is called with an argument when called from outside the seq item
1) While using second option of handshake(using get and put method in driver side), whether finish_item() in sequence is non blocking func? If yes, then how its blocking for 1st approach and non blocking for 2nd approach? 2) During 2nd approach, what will happen to rsp port? Can you please explain how port will work in both approach?
Good video... Need more to learn this channel
More to come:)
Hi Ken, Is run_test is blocking or non-blocking?
Yes, it is a blocking call as it blocks the calling thread of execution until the test finishes.
Very nicely explained..👏.I have one doubt ,you told that instance override is only applicable to components and it is not applicable to uvm_transaction,uvm_sequence etc as component consists of hierarchy but uvm_transaction,uvm_sequence don't have this hierarchy.Could you please explain how the above doesn't have any hierarchy.As I am new to this Uvm.so I need to know this.
It comes down to the diff between uvm components (drivers, scb, monitors, etc.) and uvm objects (transactions, seq items, etc). Uvm transaction / seq items are dynamic , transients and as thus their constructors only has name as an arguments whereas, components are static and exist throughout the simulation and their constructor has both name and hierarchy.
Great explanation. Very helpful. Thank you
Glad it was helpful!
Is p sequencer is only associated with virtual sequencer concept?Can you please also tell me what is the use of p_sequencer ? when will you use p_sequencer ?Here, I want to know the general use case like using p_sequencer for axi_sequencer.
To put it simply, a P-sequencer (port-sequencer) is to drive transaction to a specific port interface on the DUT.
Is p sequencer is only associated with virtual sequencer concept?Can you please also tell me what is the use of p_sequencer ? when will you use p_sequencer ?Here, I want to know the general use case like using p_sequencer for axi_sequencer.
This exploit polymorphism, which are of uvm_sequencer_base class.
m sequencer does have any other handle(cannot add) and if you want some handle you need to go with p_sequencer pointer.
To put it simply, a P-sequencer (port-sequencer) is to drive transaction to a specific port interface on the DUT.
Isn't end_of_elaboration() and start_of_simulation() essentially doing the same thing?
The end_of_elab phase is called after all of the TB components have been instantiated and connected, but before any simulation activity has begun, whereas, start_of_sim mark the start of the simulation activity like resetting, registers, DUT, etc
Why don't you recommend using virtual_sequencer, can you elaborate the disadvanatages ? What is the alternative method to using virtual_sequencer?
Virtual_seqeuncers add complexity to the TB, as you need to implement and connect both a virtual sequencer and a p_sequencer, also it has a little harder to debug because there is an extra layer of abstraction.
But exactly, what is the issue with early randomization? would be useful to elaborate possibly with an example
Early Randomization can result in the object being configured or connected in an inconsistent or invalid state. Take a testbench with a driver and monitor as an example. Both of these components have a configuration parameter that sets the largest transaction size they can support. The driver might be configured with a bigger maximum transaction size than the monitor if the driver and monitor are both produced at random with early randomization, which would prevent the monitor from correctly processing the transactions from the driver.
Nicely explained
Keep watching
Thanks for good content
My pleasure
Hi Ken, If we have a test class and if we call ::type_id::create in its build phase to create an environment class, than the environment class will be created. My questions is which part triggers the build phase of the environment class - the end of build phase of test class or the ::type_id::create function call? Is it the built phase of the environment class automatically called and what happens to the built phase of the environment class when we don't create the environment class in the build phase in test class? Thanks
When a UVM class is created, its build phase is invoked after all of its fields have been initialized but before any simulation work has started. When ::type_id::create is invoked in a test the build_phase of the environment class will be called automatically as part of the process of instantiating the environment class.
In case you are using "my_rsp", should you create it as well as "my_trans"?!
Yes because response is from the DUT with update fields.
Correct me if I'm wrong, final phase is top down and not bottom-up?
Yes , I have read it that its top down!!
It is a top-down phase
What is the main role of build phase ? we are having new() function which can do the same as build phase .. I mean the instantiation of class
Hi Majji, the build phase is part of a series of phases like run, end of elab etc which helps in segregating instanton of tb components (typically in build)phase, the connection happen in connect phase, and so on. Whereas new() is used to construct an object without using the UVM factory. In UVM we typically use create() so that we can leverage factory. In conclusion, build is just a task which groups instantiations of various tb components/objects, whereas, new() or create() commands are used for instantiation. Check out the diff b/w new & create here --> ua-cam.com/video/aC-J9QuPLSA/v-deo.html.
Thank you.
You're welcome!
Thank you.
Welcome!