Відео

Thank you.

R is not actually part of the design. It’s used as a test load. You can size R to be slightly less than Vo^2/Po.

@@powerelectronicswithdr.k1017 Now the ⛅️ become clear 👌 🙌 👏. Thanks once again for your nice explanation. 👍

Hi Vaishnaviah, I cover the development of that equation in another video. Here's the link ua-cam.com/video/6RWjz1lMUrM/v-deo.htmlsi=bZA9cXAt_8Yyj2oX&t=454. Best wishes on your design. -Dr. K

Hi Satasauu75, the PWM frequency used by the carrier really depends on the application. The carrier frequency can range from 20kHz to 100kHz. Sorry that I cannot provide a concrete number. Please note that the carrier frequency in this video is not realistic as it would be too low compared to a real application. It is for illustrative purposes only. Best wishes on your design. -Dr. K

@@powerelectronicswithdr.k1017 Thank you very much.

That's a great question. It is actually easier to illustrate if you have an Ids vs Vds graph from a MOSFET in front of you. In that graph, you will find different curves for the different valuse of Vgs. As Vgs starts to increase past the thershold voltage value, the drain current will start to increase from 0A along a straight vertical line in the Ids vs Vds graph. It will reach a value of Vgs that is not the maximum value, but the current will be at maximum value. The point will then start to move along this Vgs line (or very close to it) towards the left and begin to enter the Ohmic region of the MOSFET. Also note that the increasing Vgs curves are nearly on top of each other in the Ohmic region. Once in that region Vgs will reach its maximum value, yet the current does not increase drastically. The Miller plateau is the region where the point is moving from the right to the left in the Ids vs Vds curve at a near constant Vgs value. I do hope this explanation helps, but it is much easier to visualize with a point moving in the Ids vs Vds graph. Best wishes on your design. -Dr. K

Hi Praveendveen. I'm assuming you mean delta Vo, the output voltage ripple across the load of the converter. The output voltage ripple is computed from the current ripple through the inductor, the capacitance value and the switching frequency. I have two other videos on sizing the inductor (ua-cam.com/video/tMJRwq8CWeI/v-deo.htmlsi=q6fF0a4ahmQv2ArZ) and sizing the capacitor (ua-cam.com/video/6RWjz1lMUrM/v-deo.htmlsi=XGdblthZpY6DGYKd) for the buck converter. Best wishes on your design. -Dr. K

Hello Fatihe.1338, My handwriting is not good. That should be VDS(D) and D stands for the datasheet. The switching times can be very difficult to obtain accurate values as these times change based on the load requirements and the DC bus supply. Here is a good video from TI regarding the info on a MOSFET datasheet as it relates to turn-on/off times www.ti.com/video/series/mosfet-101.html#

Great question. Let's start with the AC term of the current ripple. This current ripple is triangular shaped and therefore the RMS (effective) value is peak amplitude divided by the root(3). Recall for sinusoidal it is peak amplitude divided by root(2). The peak amplitude of the AC term is delta_Io/2 because delta_Io is the total peak-to-peak value. In order to get the power loss in the inductor, you use the square of the DC value of the current and the square of the RMS (AC value of the current). The square of the RMS value will be (delta_Io/2)^2 divided by 3. This results in delta_Io^2/(4*3). Often times, we can ignore the AC power loss in the inductor as it is much smaller than the DC loss. Hope this explanation helps. Best wishes on your designs. -Dr. K

Depending on the type of VFD, more often than not you will find a PWM based inverter. Six step inverters are typically used for simpler motor drives or heater driving systems and such applications can tolerate the valleys (AC ripple) on the DC bus. Both PWM based inverters and 6-step inverters use bulk capacitance on the input (DC bus) of the DC/AC inverter system. This capacitance is physically placed very close to the switching devices to minimize the effect of lead inductance. The bulk capacitance has multiple functions. One is to provide charge quickly for applications that have large start-up current requirements. Another function of the bulk capacitance is to provide a level of "hold-up" time should there be a momentary loss of input. The bulk capacitance is sized for the output power, amount of hold-up time, and minimal operating voltage. The valleys associated with the AC/DC ripple can be account Hope this helps! Best wishes on your design.

What would you like to see? I do need to do a series of videos on 3=phase PWM inverter design along with the AC filter design equations.

You are welcome. Best wishes on your design.

Thank you.

Yes, good observation. Often that diode is replaced with a MOSFET. This is called a synchronous converter. It has lower loss (improved efficiency) but requires a more complex controller. There is still switching loss in the MOSFETs, but if the frequency is low enough, the overall loss will be better. There are converters such as resonant converters that utilize zero-voltage, zero-current (ZVZC) conditions and have even better efficiency. Best wishes on your designs. -Dr. K

@@powerelectronicswithdr.k1017 thanks for your kind response! Sync buck do need a complex controller, that's why I mention the dead-time. During the dead-time, the body diode of MOS will conduct firstly. That will cause an extra power loss: Vdiode✖️Io✖️（dead-time/T）, but body diode dosen't have a ton and toff time, it exists automatically, so I think the rectifier MOS will cause a body diode power loss, but has almost no switch loss.

Lower loss when the diode conducts. The other selection would be a fast recovery diode. Many converters are also synchronous and use a MOSFET instead of a diode. Great question and best wishes on your design.

Hi! The links for the equations can be found in the video description. Best wishes. -Dr. K

Great question which applies to high-side driving of typically a P-channel MOSFET. The answer is yes. However, the switching frequency range is relatively broad and will partially determine the value of boot-strap capacitor used. As an example, it is impossible to never switch because the boot-strap capacitor requires charge and this capacitor charges up when one side is switched to ground either through the driver or through the low-side switch. Once charged, the boost-capacitor can then be used to drive the MOSFET and acts like a floating voltage supply. However, the capacitor will eventually discharge over time and the result is Vgs will slowly decrease to an in operable point. If the switching frequency is to high, the boot-strap capacitor never fully charges up or takes too long to charge. Often the high-side gate drive datasheet will provide information on selecting the boot-strap capacitor based on your switching frequency. Best wishes on your design. -Dr. K

@@powerelectronicswithdr.k1017 thanks for perfect explanation. one more question about gate drive. Gate drive require high current for a moment ,(say 500 mA), due to Cgs. If we use bootstrap, does bootstrap capacitor can deliver such a high current?

Yes, that is correct. I do not show the gate-driver circuitry or control for this. That would be another video. N-channel MOSFETs require special circuitry for high-side driving. There are h-bridge topologies in which the two high-side switches are P-channel MOSFETs. This makes for easier switching. Best wishes on your design. - Dr. K

Hi Ziadfawzi. Great question and the answer is that it depends. For example, will you try to maintain a constant output power at all voltage ranges? If so, then the output current will be maximum at the smaller output voltage values and minimum at the larger output voltage values. It would be a good practice too look at both extremes and see which values will "stress" your components the most. Sorry it is not as easy as just the highest output voltage. Best wishes on your design. -Dr. K

Hi Jviccii, the resistance is not part of the design of the Buck Converter. It is an easy way (although not always accurate) to implement a load on the power supply. You can set the value to Vo/Io. However, please take caution as not all loads are purely resistive. Great question and best wishes on your design. -Dr. K

Hi Gan-rc2im, yes you are correct. I am using these terms liberally. On the datasheet, the rise time is actually the amount of time it takes to turn the MOSFET "off". This is the time duration where Vds rises from near 0 V to the supply value Vdc. The fall time is the duration it takes to turn the MOSFET "on". The is the duration where Vds drops from Vdc to near 0V. Please note that the datasheets use very specific testing parameters and your application of rise and fall times will vary. Great observation and thank you for watching. -Dr. K

Hi, I developed those graphics using MS Visio, MS Power point and some of the simulations were done in LTspice.

Lol... You do know you can skip past the introduction. Have a great day MrSummitville and best wishes on your designs. - Dr. K

@@powerelectronicswithdr.k1017 LOL - You do know, that adding crap noise to your video does not make it better? Have a nice day...

Yes, that would be correct. The units would be 100 Vpp (volts peak-to-peak) or 50 Vp (volts peak).

You’re welcome.

Often one assumes the load is resistive and because the output voltage is relatively constant ( with the exception of the voltage ripple), the average output current is constant. The output capacitor is therefore used to store and provide charge to help maintain that constant voltage assumption. Thank you for the question and best wishes on your design. -Dr. K

Thank you.

Pablo, YES! Great catch. The voltage should be in the range of -0.5V to -0.65V. Luckily we have a low forward voltage drop and it will not impact the results drastically. Also, you are correct, the average value of Vds during that period will be (Io/D)* Rds and that is 2/3*Rds. Best wishes on our design. -Dr. K

@@powerelectronicswithdr.k1017 thank you very much

That's actually the peak value of the current on the secondary side. This comes from the computation of the average value of a fully rectified sine wave. The average value of |Apk*sin(wt)| is 2*Apk/pi, where Apk is the peak value. In this case it Is. Solving for Is using the average, one gets Io*pi/2. If only 1/2 wave rectification is used, then the equation would change to Io*pi. Hope this helps. Best wishes on your design. -Dr. K

@@powerelectronicswithdr.k1017Thank you Dr. K! That makes more sense. I think you mispoke in the video by mistake and I took it literally😅😂. Thank you for your lecture too! Have a great day!