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Rho Vector
Приєднався 14 жов 2020
Polar NRZ Signaling in Simulink MATLAB
NRZ & RZ Simulation Project files in GitHub
github.com/rhovector/Simulink_Communication_Systems
1. Design in Simulink MATLAB 2017
2. Communication System Toolbox
github.com/rhovector/Simulink_Communication_Systems
1. Design in Simulink MATLAB 2017
2. Communication System Toolbox
Переглядів: 5 029
Відео
Half Sinusoid and Raised Cosine Pulse using Simulink MATLAB
Переглядів 3,5 тис.3 роки тому
HS & RC Pulse Simulation Project files in GitHub github.com/rhovector/Simulink_Communication_Systems 1. Design in Simulink MATLAB 2017 2. Communication System Toolbox
QPSK using Simulink MATLAB
Переглядів 39 тис.3 роки тому
QPSK Simulation Project files in GitHub github.com/rhovector/Simulink_Communication_Systems 1. Quadrature Phase Shift Keying communication system 2. Design in Simulink MATLAB 2017 3. Communication System Toolbox
DPSK using Simulink MATLAB
Переглядів 10 тис.3 роки тому
DPSK Simulation Project files in GitHub github.com/rhovector/Simulink_Communication_Systems 1. Differential Phase Shift Keying communication system 2. Design in Simulink MATLAB 2017 3. Communication System Toolbox 4. Basics of Simulink operations
Layout Design of Two-Stage Operation Amplifier (Opamp) in Cadence Virtuoso
Переглядів 14 тис.4 роки тому
OPAMP Layout Project files in GitHub github.com/rhovector/Cadence_Virtuoso_180nm_Projects 1. Layout design for OpAmp in 180nm 2. Verification of DRC and LVS
Layout Design of Common Source (CS) Amplifier in Cadence Virtuoso
Переглядів 3,4 тис.4 роки тому
CS-Amplifier Layout Project files in GitHub github.com/rhovector/Cadence_Virtuoso_180nm_Projects 1. Layout design of CS Amplifier in 180nm 2. DRC and LVS verification
Layout Design of CMOS NAND Gate in Cadence Virtuoso
Переглядів 9 тис.4 роки тому
NAND-Gate Layout Project files in GitHub github.com/rhovector/Cadence_Virtuoso_180nm_Projects 1. Design Layout of CMOS NAND in 180nm 2. Performing DRC and LVS
Layout Design of CMOS Inverter in Cadence Virtuoso
Переглядів 10 тис.4 роки тому
Inverter Layout Project files in GitHub github.com/rhovector/Cadence_Virtuoso_180nm_Projects 1. CMOS Inverter Layout Design in 180nm 2. Perform DRC and LVS
Introduction to Layout design in Cadence Virtuoso
Переглядів 6 тис.4 роки тому
1. Basics of Layout Rules 2. Structure of MOSFET 3. Layout of MOSFET in Cadence Virtuoso
CMOS Two-Stage Op-amp simulation in Cadence Virtuoso
Переглядів 10 тис.4 роки тому
Steps to simulate an opamp in cadence virtuoso with 180nm technology.
CMOS Two-Stage Operational Amplifier schematic & symbol in Cadence Virtuoso
Переглядів 12 тис.4 роки тому
OPAMP Schematic Project files in GitHub github.com/rhovector/Cadence_Virtuoso_180nm_Projects Steps to design a two-stage opamp and its symbol on cadence virtuoso with 180nm technology 0:00 Intro 0:12 Op-Amp Schematic creation 6:55 Op-Amp Symbol creation
CMOS CS-Amplifier simulation in Cadence Virtuoso
Переглядів 5 тис.4 роки тому
CS-Amplifier Simulation Project files in GitHub github.com/rhovector/Cadence_Virtuoso_180nm_Projects Steps to simulate the CS amplifier in 180nm technology
CMOS Common Source Amplifier schematic & symbol in Cadence Virtuoso
Переглядів 3,1 тис.4 роки тому
CS-Amplifier Schematic Project files in GitHub github.com/rhovector/Cadence_Virtuoso_180nm_Projects Steps to design the schematic and symbol of a Common Source (CS) Amplifier in 180nm technology.
CMOS NAND-Gate schematic, symbol and simulation in Cadence Virtuoso
Переглядів 20 тис.4 роки тому
NAND-Gate Schematic & Simulation Project files in GitHub github.com/rhovector/Cadence_Virtuoso_180nm_Projects Steps to develop a schematic on CMOS NAND Gate in 180nm technology. Procedure to simulate the design in Cadence Virtuoso.
Simulation of CMOS Inverter in Cadence Virtuoso
Переглядів 8054 роки тому
Inverter Simulation Project files in GitHub github.com/rhovector/Cadence_Virtuoso_180nm_Projects Steps to simulate the schematic designed on the inverter in Cadence Virtuoso. The propagation delays of the inverter in 180nm are discussed.
CMOS Inverter symbol in Cadence Virtuoso
Переглядів 1,8 тис.4 роки тому
CMOS Inverter symbol in Cadence Virtuoso
CMOS Inverter Schematic in Cadence Virtuoso
Переглядів 1,8 тис.4 роки тому
CMOS Inverter Schematic in Cadence Virtuoso
How to add instance in Cadence Virtuoso
Переглядів 4,2 тис.4 роки тому
How to add instance in Cadence Virtuoso
How to create a library in Cadence Virtuoso
Переглядів 8 тис.4 роки тому
How to create a library in Cadence Virtuoso
35947 Donavon Ways
ua-cam.com/video/KdLoMi-fIU4/v-deo.html for Simulink Simulation of QAM passband signaling to measure the SER (Symbol Error Rate) ua-cam.com/video/4cQChi4n1UY/v-deo.html for MATLAB Simulation of QAM passband signaling to measure the BER (Bit Error Rate)
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Hi Sir! This video was so useful. It will be really helpful if you can also post how did you calculate these W,L and other values. Thank you !
Is this two stage open loop comparator?
bro please improve video clarity its too blur
how did you get the cadence software
m_F6Yw7f4GZAlqQDbENKozUG.h what is this type of error when i try to run ,kindly guide me why its giving errors
How to fix font size in cadence library?
Could you show how to do this on the 2023 Matlab simulink please?
Ya 😊like
thank you so much, indians are the best ! <3
Great explanation
I think oxide layer doesn‘t represent oxide grown above Pimp in this PDK but cut in the oxide. Opening where there is no oxide. Also I think oxide is not gat oxide but shallow trench insulation-field oxide
when i click on detach body its giving error
could you also explain ofdm ?
Thank you
Sir, can you please provide D flip flop using this NAND gate
VERY GOOD EXPLANATION ,THANK YOU
I e-mailed you. How can I download 180nm library file?
How to Download GPDK - 180nm PDK
Which technology library you are using
GPDK180
Great job! I always thought cosine was real and sine was imaginary can you pl double check. otherwise this is fantastic and helps us understand the concept better.
Great video...low quality 480p
what is the output we get from layout design apart from getting av_extracted view
please design the 4 bit asynchronous down counter in cmos vlsi design
bhai bhot sahi
Vdd(S) Vo(D) Vdd(S) Vss(D) mid(S,D) Vo(S) connect Vo, gates, Vdd, Vss
Can you please send your email id any say why model is not working ,I have build the same model.
Nice 👍👍
What are u saying in 3:52 until 4:04 i cannot interpreted it clearly. can someone rewrite in reply section below?
Thank you for the excellent insightful video
Very helpful video. Thank you
Sir please help me sir, Where can I find pass transistor sir I mean that transistor name sir like bsimp4 like that sir. I have Shannon adder by using pass transistor sir but I don't where it is sir
helpful👍
Hi! Thank you very much for this series of videos on virtuoso! I am facing some issues with simulation of the two stage opamp. It does not go into saturation when the input sine wave is applied. Instead, the output is a sine wave with a negative dc component. Could you please suggest potential mistakes to look out for?
I am also facing the same issue and also the gain is 28dB... even applying all the same parameters I am not getting 75dB gain.. Please help us out sir🙏
I think in the schematic of OP-AMP, the current input node has to be connected to the gate of MOSFETS which width is 4.5um and length is 1um
ON THE RANDOM INTEGER BLOCK I NEED 3 BITS SO SET SIZE IS 8 BUT IT DOESNT WANNA SIMULATE
its qpsk , it transmits 2 bits simultaneously so you cannot 3 bits
what changes i have to do to make it unipolar or bipolar?
Thanks, it's a really helpful tutorial.
Which nano meter
mam what does filter span in symbols represents in raised cosine block? i am confused about how to select that parameter.
For me i can't get 2 ports in scope why
How to get neat graph, i am unable to get it plz help me
Good job man...
thank you so much
Fantastic Job. Really helpful
Inefficient explanation, everyone knows how to place components and all. Please explain what is QPSK, how does modulated wave works from given input wave in detail.
first thank her, man
No, horrible comment, out of place and time, this video was straight to the point, if you are a newbie, watch other videos first. This video is for advanced people, novices, keep your comments where the sun doesn't reach them.
What is gain of this circuit?
no idea o f layout my friend