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GT Station
Nepal
Приєднався 7 бер 2016
Experiencing glass walk for the first time in Pearl TV Tower, Shanghai. #glasswalk #shanghai
Experiencing glass walk for the first time in Pearl TV Tower, Shanghai. #glasswalk #shanghai
Переглядів: 20
Відео
Beautiful night view of Pearl TV tower located in Shanghai, China. #pearltvtower #shanghai #travel
Переглядів 324Місяць тому
Beautiful night view of Pearl TV tower located in Shanghai, China. #pearltvtower #shanghai #travel
Trying octopus for the first time in Chinese street.
Переглядів 72 місяці тому
Trying octopus for the first time in Chinese street.
Live video of taking pearl out of oyster, in Hangzhou, China.
Переглядів 552 місяці тому
Live video of taking pearl out of oyster, in Hangzhou, China.
Qiantang river, Hangzhou, China. Local call it a mother river.
Переглядів 162 місяці тому
Qiantang river, Hangzhou, China. Local call it a mother river.
Atif Aslam Live Concert in Nepal. Pehli Dafa song.
Переглядів 4,3 тис.4 місяці тому
Atif Aslam Live Concert in Nepal. Pehli Dafa song.
Atif Aslam Live Concert in Nepal. Dil Diya Galla song.
Переглядів 4,2 тис.4 місяці тому
Atif Aslam Live Concert in Nepal. Dil Diya Galla song.
Atif Aslam live concert in Nepal. Tera hune laga hu song.
Переглядів 1,6 тис.4 місяці тому
Atif Aslam live concert in Nepal. Tera hune laga hu song.
Arjit Singing Nepali song in concert in Nepal.
Переглядів 2,1 тис.9 місяців тому
Arjit Singing Nepali song in concert in Nepal.
half subtractor in vhdl using vivado
Переглядів 6402 роки тому
VHDL code for various combinational circuit is given in the link below. drive.google.com/drive/folders/1aim_r3lw8NtrqrGWDW2LFL8fqZl9RSPu?usp=sharing
VHDL introduction and NAND gate using Xilinx Vivado ( Computer architecture lab for CSIT students)
Переглядів 7112 роки тому
VHDL code for various combinational circuit is given in the link below. drive.google.com/drive/folders/1aim_r3lw8NtrqrGWDW2LFL8fqZl9RSPu?usp=sharing
half adder and full adder in VHDL using Xilinx Vivado
Переглядів 7 тис.2 роки тому
half adder and full adder in VHDL using Xilinx Vivado
associative memory or content addressable memory(CAM)
Переглядів 1232 роки тому
associative memory or content addressable memory(CAM)
memory organization part 1 ( Memory hierarchy, RAM, ROM Module, mapping of memory
Переглядів 582 роки тому
memory organization part 1 ( Memory hierarchy, RAM, ROM Module, mapping of memory
input output organization part 2 ( interrupt, daisy chain, parallel priority interrupt, DMA, IOP)
Переглядів 532 роки тому
input output organization part 2 ( interrupt, daisy chain, parallel priority interrupt, DMA, IOP)
input output organization part 1 ( peripheral devices, polling, interrupt, daisy chain interrupt..)
Переглядів 982 роки тому
input output organization part 1 ( peripheral devices, polling, interrupt, daisy chain interrupt..)
Digital Logic Revision 4 ( Sequential Circuit part 1)
Переглядів 412 роки тому
Digital Logic Revision 4 ( Sequential Circuit part 1)
Digital Logic Revision 3(Combinational Circuit 2)
Переглядів 352 роки тому
Digital Logic Revision 3(Combinational Circuit 2)
Digital Logic Revision 2 (Combinational circuit 1)
Переглядів 442 роки тому
Digital Logic Revision 2 (Combinational circuit 1)
Digital Logic revision 1 (Number System)
Переглядів 882 роки тому
Digital Logic revision 1 (Number System)
Digital logic lab part 7(demultiplexer)
Переглядів 782 роки тому
Digital logic lab part 7(demultiplexer)
Digital logic lab part 6 (multiplexer 74153IC) class version
Переглядів 802 роки тому
Digital logic lab part 6 (multiplexer 74153IC) class version
Digital logic lab part 4 (half adder) unedited version
Переглядів 772 роки тому
Digital logic lab part 4 (half adder) unedited version
Digital logic lab part 5 (full adder) unedited version (class version)
Переглядів 602 роки тому
Digital logic lab part 5 (full adder) unedited version (class version)
Digital logic lab part 3 (7486 XOR gate)
Переглядів 703 роки тому
Digital logic lab part 3 (7486 XOR gate)
Digital logic lab part 2 (7432 IC for OR gate)
Переглядів 1363 роки тому
Digital logic lab part 2 (7432 IC for OR gate)
Digital logic lab part 1 introduction(unedited)
Переглядів 1613 роки тому
Digital logic lab part 1 introduction(unedited)
yeah think ill skip that
😂😂😂too ashamed and embarrassed
@@DK-ev9dg 😂😂😂 your comment doesnt make sense 😂😂🤣🤣🤣
@@xo121w your don't either. Make the frocking clear.if you're China hater or not?
Here is the link to the PDF of all the lectures. drive.google.com/drive/folders/1vt3C86ofW7szgF4CP7QDFSLLdQeTgAHx?usp=sharing
can you please send notes of all the chapters if possible? you can have my whatsapp number also if you need actually I have exam on 12th moreover, i don't know the language you are speaking in the video as I am from North India(Delhi)😊😊
❤❤❤❤❤
Please Upload Full Concert Video
Masterpieces performence❤
Wow ❤
Wow❤
My favorite singer❤❤
ATIF ASLAM PURE VOICE WITH BEST TEXTURE QUALITY ❤❤
MESMERIZED PERFORMANCE❤
EVEN IN BETTER VOICE QUALITY INSTEAD OF ORIGINAL ONE❤
If the title is in English, make the video in English or explicitly mention the language in the title.
Wow ❤
wat e fuck u talking???
sir sabai chapter ko ek ek ota playlist banaidinuna please. It's a request.
Thank you sir. Appreciate it.
Sir yo DL ko pdf files pathauna milxa?
I have already uploaded in the Google classroom
@@gtstation6243 xaina google Classroom ma ta
Pdf??
drive.google.com/file/d/19EpUrkEQwL3g8_GXHvaldQ5SBW6KDXQi/view?usp=drivesdk
Yo Master slave JK flip-flop asynchronous circuit ma set preset wala setting chai 2 ta include garna parxa ki Master circuit ma mtrai garda hunxa
sir i didnt understand in full addder implementation by half adder that how carry has z(x xor y)+x.y
very much helpful
Tapaile logic diagram ma oRing complement use gareko thauma direct nand gate use garna mildaina?
tei garne ho .. complement ORing vaneko NAND ra complemented ANDing vaneko NOR .. tei ta vaneko xa hoina ra?
Kun college ho??
Use head camera plz and be safe
Nice ride man!!!!
Bishnu Tiwari thanks yar
kati ramailo chha hai , sath ma badai pani