Відео

Thank you. I have a question. Can i swap Pins of my DDR3 and zynq 7000 ? Xc7z020-2clg 484 and DDR3 MT41k128m16jt-125 ? If yes, which Pins ? Thanks a lot

🤘🤘🤘🤘🤘🤘🤘

Gz.. in the beginning I thought you just bump in an of the shelf card, but you also designed that on ya own.. Respect papi

the 16bit eater guy

planning on throwing freedos or linux on it? :D

Thank you for the video. Do you need to have one of the inner layer as ground plane when both top and bottom also works as a ground plane?

Thank you for your sharing！

This has been very interesting to watch as a series, a bunch of "aha moments" for me personally as I'm not at all into this level of design (yet). I went ahead and ordered a few pcb's from the gerber files and the plan is to TRY (and likely fail) to 386-upgrade the Tiny Turbo 286 upgrade used as another upgrade for the 8088 CPU on the A2088XT bridgeboard in my Amiga 2000 :D. Yes it's an upgrade on an upgrade on a PC in an Amiga! Also is there a BOM for the build of the pcb?

Thanks a lot ❤

Great video! I also plan to use the same 8 layer stackup as yours with ZYNQ. But I think the trace width for 50 ohm impedance, which is calculated to be around 0.17mm, might be difficult for routing DDR signals. May I ask what is the trace width you used in this PCB? Thanks!

Hello. Thank you How can i design and rout ddr3 module on the same ZYNQ you have explainded here ?

Very well done video. You deserve more subs for this quality

Review Xilinx xapp974. I didn't see you add the SPI device to the Xilinx impact chain (You will see FLASH attached to your device. See page 15). You can follow the steps outlined in xapp974 and run ISE 14.7 impact software standalone without the complete Build IDE. If that fails you can modify the "Picoblaze NOR FLASH Programmer for the Spartan-3E Development Kit" sample application and program the SPI through a serial connection, (you will have to use a logic to RS-232 converter).

Nice tutorial

Bit of a tangential question, but what digital microscope do you use?

A bit of logistics advice - assign numbers to all boxes which will store parts, and create an Excel sheet listing all components with the box number where they are stored. Also write box number on component label to make sure you put it back into the same box. Otherwise you will be spending insane amount of time searching for parts before you know it. Ask me how do I know this 😊

I love your videos!

Don't know much about Spartan-3, but in 7 series and newer indirect flash programming works like this - FPGA is programmed with a special bitstream which is essentially a JTAG to QSPI bridge, it allows talking to flash from PC, and then programmer sends a bunch of commands to flash which include a bitstream itself. This bridge also supports reading back contents of flash, which allows programmer to verify that programming was successful, but you can also just read flash contents and save it to a file. The latter is useful when working with devboards as you can save original bitstream before overwriting it in case you ever need to restore it back the way devboard was shipped.

Modern Xilinx tools also work better in Linux, and for some things - like building Petalinux images for Zynq and Microblaze, Linux is required. So I would suggest you to get comfortable with it if you aren't already 😀

Indirect programming of qspi flash makes a lot of sense since it allows you to eliminate extra connections and thus reach higher frequency since connection essentially becomes a point to point with no stubs or branches. And since all modern-ish Xilinx FPGAs are SRAM-based, they can be reconfigured unlimited number of times with no downsides.

Just wanted to say this ist Just great work. I enjoy your videos. Thanks for Sharing.

For assembly - it's best to assemble the entire side of a board at the same time, you will need a stencil for this, but it's much faster than soldering components one by one. In case of this board I would assemble the bottom side first, and then make standoffs from M3 bolts and nuts and assemble the top side. Don't worry about components from the bottom side falling off - surface tension of molten solder is going to hold them in place unless they are super heavy. I've had components up to QFN48 on a bottom side, and they did not go anywhere after top side reflow.

I think the AY is broken, I can barely hear it.

Funny with JLC, when you get the $2 specials, it's cheaper to order two separate orders than combine. I usually just get standard shipping rather than courier, and they're under $5 delivered to Australia. What's crazier is that I can't even ship a similar (smaller) package within Australia for that.

It would be interesting to see and compare what other online PCB manufactures would quote.

It's hard to follow what's going on the screen. You might want to lower the resolution of the screen to make it more readable.

Nice, almost done! What’s the reason the HDMI is positioned like that?

Regarding fan PWM - since you have free GPIOs, you can use one of them to drive a MOSFET which would control the fan. Make sure it defaults to always-on when there are no control signals from the CPU via a pullup, and don't forget to add a reverse-protection diode across the fan to make sure fan coil's inductance won't destroy the MOSFET.

I prefer assembling my prototypes manually. It can be a pain to manually place 200+ components per side before reflow, but I still enjoy the process, and my wife helps me out when I need to take breaks. It does take quite a bit of time (about 5-6 hrs per side with 200-300 components, most of which are 0402s), so I usually do it over the weekend.

MDC/MDIO form a management interface for Ethernet PHY, it uses signalling somewhat similar to (but not compatible with) I2C, and is used to access Ethernet PHY's registers to configure all aspects of their functionality. Part of them are standardized, but many are device-specific. You can read more about this interface in IEEE 802.3, clause 22.2.4. This bus is very slow (< 1MHz), so you don't have to worry about routing it - as long as pins connect - it will work.

DDR3 has a minimum frequency of 303 MHz. You can't run it slower than that - at least according to specification. And I wouldn't worry about it too much anyway - 533 MHz is fairly slow by DDR3 standards (it can go as high as 933 MHz per JEDEC), so you can get away with some amount of sloppinness 😀

You will definitely need a fan, unless your heatsink is going to be giant 😀 Just run Linux 😁

I had to slap together a GPS board and made the mistake of routing TX to TX and RX to RX. Unfortunately it's relative, unlike MISO/MOSI designation. I had to cut traces and cross the connections. Yes, I literally had "measured once, cut twice", lol. Lesson to make absolutely sure before cutting the board. But also cheap insurance to have zero-ohm jumpers to make it easier to correct any crossed connections.

Cool progress. And yes, slow down your DDR if you have issues. Getting it to run at full spec speed can be some black magic.

What’s that drawing board software called at 13:58?

I still think you've got passives waay too close to the SoC for manual assembly. As a rule, I always have a keep-out area around major devices of at least 5 mm on each side, as this will make things MUCH easier should you ever need to rework these devices. And I still have my suspicions regarding those nearby parts interfering with heatsink/fan installation - see if you can move all these parts on the bottom side of the board. Larger decoupling caps are not very location-critical, so it's OK to move them farther away from the SoC if needed.

Awesome work. And here I am struggling to route my RP2040 project :D

Regarding address bit swapping - what you are reading refers to "soft" memory controller implemented via MIG (Memory Interface Generator). For Zynq PS DDR controller address pins are fixed, and so they have to be routed to corresponding pins of memory devices.

Wow, absolutely amazing all the progress you're making! I'm definitely looking forward to seeing the finished product! I don't think you can do bitswapping on the DDR address lines; according to the datasheet it seems there are different functions depending on mode. Well, maybe some can? A bit hard to figure out, maybe not worth the risk. The other thing is that vias can be stubs when connecting to inner layers, so backdrilling or microvias are used to prevent this on the highest-speed interfaces, to prevent signal degradation. A better way to prevent this is to route your highest speeds on the top and bottom layers, then there's no stubs to worry about. I think the only place it may impact your design in the DDR interface. It might not really matter on your implementation, but would still be good practice.

Sounds even more epic than movie version it self)

don't forget to add an HDMI retimer ic. Not only do they help with stable signal levels leaving the board, but it along with trace matching ensures you have a clean signal with minimal signal skew.

4:00 is the stackup dimensions on the right correct? Looks to be asymmetric, which is unusual. Unfortunately, I don't see the 8-layer stackup at JLCPCB.

I really like your videos

Hey, just started watching you video. One thing i noticed (not sure if intentional) but you placed a lot if vias in your decoupling-cap pads. that is generally not a good idea, because it can wick away solder - but that depends on your pcb manufacturing (filled vias).

Wow, this got really complicated really fast. Keep up the good work!

Perhaps consider using a TPS2115A for your dual 5V power inputs. It will "power OR" your inputs and you will not need to manually set a jumper. Among its many benefits is that you can also use it to set a current limit.