Відео

Hello Sir, Can u share that Word document.

Why cant we set asunc between 2 clocks in logically exclusive

first assignment script set var2 [list ] set var3 [list ] set a 0 set var [list a123xy 124 124xy24 567 90 xy34] #puts $var set i jdjdj7 lappend var 84hdn hdd32 lappend var $i set j 637hdjd set var [linsert $var 2 jnfnn 48348ff] set var [linsert $var 2 $j] foreach var1 $var { if {[regexp "^\\d" $var1]} { puts $var1 lappend var3 $var1 set var2 [linsert $var2 $a $var1] incr a } } puts $var3 puts $var2

Good information

Not real.

who here from twitter

reel

❤

hi. At 5 :20, why will the U3 flop will not go to meta stable state along with U2 since the same Async_reset signal is given to both flops ?

"Fantastic video! The explanation was clear and detailed, Keep up the great work!

salay tera code nai challra

Shouldnt Txd be pulled high at the end? Thats what the waveform suggests.

very nice!

can you discuss a problem with what happens if the latch is a Look-up Latch? FF1 to latch Td is 40ns and latch to ff2 is 60ns, Total Period is 100ns. How will this scenario work?

Thanks!!! It would have been great with the explanation too, of the set_mulcycle_path, wich includes the -from option, but wihtout the -to. Considers every flipflop connected to that register?

Very good video ....😃

Sir iam doing btech in ece branch some tips please

Should PLL clocks from same PLL be excluded from each other?

thank you neel gala sir for session

Sir multiple cycle value of hold always zero or not?

Hello sir, thank you for this video, i am 7th sem student , i have designed a riscv 32 bit 5 stage pipelined verilog code for processor, would u mind helping me out with guidance for hardware implementation on fpga sir , its a sincere request sir for paid help

nice video any workshops please inform in the channel

Telegram name what is it sir

Hello Vikas Sir, since the clock tree is common after clock mux, the tool will try to meet timing between clk1 and clk2 on FF1 which would be incorrect? Clk1 to F1 to F2 (clk2) and Clk2 to F1 to F2 (clk2) is valid but because of mux it have path from clk1 F1 to clk2 F1 and vice versa, then how do you constrain these ?

I can't understand what you saying 😢

Good explanation for integration of Arduino libraries to the Jhejas controllers. This can replace Arduino usage. I was trying to find the baremetal codes for the GPIO and UART. Can you also share some baremetal codes which we can setup and compile using a Makefile.

😅

Sir its very good session, pls upload the left part of metastability also on UA-cam.

how can i do clock gating in sta ?? i read the manual,but i didnt get change in the power give me correct way of doing it in opensta

are there any tool which perform GBA? I assumed all tools perform PBA only.

video failed to provide an explanation when you would 2-stage and when you would use 3-stage. its again the same general equation that mtbf value should be low. now mtbf value will be low for both 2-stage and 3-stage. but how to decide which one to pick?

For chnaging the state from start to trans FSM states, what is the input, i.e on what condition the state is changed? You told the tick signal is set from the the baud rate genereater, so is it constant? Can you explain this?

Wow .. very good

💥 'Promo SM'

How are we constraining logical exclusive clock?? I know about set false path command. IS there any other way also?

Sir plz upload one session with the Google's bard too . Bard provides 3 alternative codes which can be the answer to the given query .

what if timing is not met in PBA too

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Thank you mam

फभ

Very insightfull... I remember kinda being excited and awestruck during my first day & not really interacting with people.. Haha. 😂😂

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@vlsideepdive Can you tell me how to match the file extensions .. I have a regex {png|bmp|jpeg}.... the disadvantage of this reqex is that it matches the invalid input "pngbmpj" as well... Do you know any better regex pattern for matching valid extension?

Thanks for the lecture. Please help clarify this query. The max delay with which data can arrive at latch is described to be the transparent period of latch - which I understand , but wouldn't this also be dictated by the delay of next stage combinational cloud i.e it should be able to meet setup for next flop ?

great to know about how rtl design engineer feels.

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