Відео

You are right. Looking back on it, that whole github repo is a bit of a mess. I don't think I'll change the videos, but I may fix up the repo, including better documentation of pins. I need to recall why I changed pins on the rpi... Perhaps not all pins are capable of being set to open drain.

Thanks. I'm glad you enjoyed it. I think learning some Verilog (or VHDL) is good, and these cheap FPGAs are a great vehicle for that. But I also agree that modern microcontrollers are so capable that many projects do not require an FPGA. One area where FPGAs shine is implementing peripherals that operate autonomously alongside a microcontroller. For example driving addressable LEDs requires fairly tight and consistent timing. It's nice to have that decoupled from software in case the microcontroller has something serious to do along with controlling the LED. Cheers.

Sorry, I do not see that. My Tang Nano 20K programs reliably. I use default frequencies and do not have to press a button. I can load the design to SRAM (which is not permanent) or to flash (which is). I can program it using the latest Gowin educational tools on Windows (but not Linux). On Windows, the only problem is that sometimes I need to select Edit/Cable Setting/USB Cable Setting and let the tool find the device. On Linux Ubuntu 22.04 openfpgaloader works very reliably. See my video on getting started with the Tang Nano 9K for more on openfpgaloader. Best wishes

@@electronics.tinker It was my mistake. I thought multiple files could be programmed at once, but they all need to be loaded individually.. So I just had to hold down S2 while powering up and ensure that only one file was checked in the Gowin programmer. The errors the programmer gives back tend to be a bit misleading. ..and yeah, I'm using Windows.

You are right. I had not noticed that misspeaking. Cheers.

I get the same thing: Qt: Session management error: Authentication Rejected, reason : None of the authentication protocols specified are supported and host-based authentication failed It has not caused me problems. I think Gowin tested their Linux-based tools on a version of Ubuntu even older than 22.04. As you use newer versions of Ubuntu, problems get worse. Gowin's strategy for supporting Linux is not very good. Frankly, the Gowin tools work a lot better on Windows (at least Windows 10-- I don't have a computer capable of running Windows 11). I have started running the Gowin tools mostly on Windows as the path of least resistance, and I run Ubuntu 22.04 under Windows Subsystem for Linux (WSL2) on the same machine. This allows me to continue to use Ubuntu for software builds. I prefer Linux to Windows, but Gowin does not make it easy! Cheers.

Glad you liked the video. I don't know much about signal processing, though.

Yes, there are circumstances in which having a hard core makes sense. Imagine that the FPGA is being used to implement a high-speed peripheral, a computational accelerator, or both. Also, assume that these are to be memory-mapped peripherals of a controlling core. The number of signals coming out of the core is pretty high. For that reason alone, it can make sense to integrate the core into the FPGA. I think this is more likely in larger FPGAs where the you need may be even more sophisticated core than an M3. Integrating a a hard Cortex-A53 (to run Linux), hard DDR controller, hard ethernet, etc. is possible (actually easy to find) on larger FPGAs. The FPGA becomes a complete Linux-capable system-on-a-chip connected internally to the FPGA resources. More complex interconnects than APB will be used so the signal count and frequency will be high. Also , some of the signals may be differential. The smaller the FPGA, the less this makes sense (at least on average). Cheers.

Glad you found it useful. I had noticed that there is not too much information out there on the M3 on the Tang Nano 4K.

That's good information, thanks. I decided that the path of least resistance is to run Gowin on Windows, though.

it work for me too in Ubuntu 24.04.1 LTS, thanks very much

That would be much harder. Simple, cheap analog multiplexers are not fast enough. Also producing quadrature LO signals at such high speeds would need different techniques.

You are using an open source tool chain which has its advantages. But. using Gowin hard IP blocks might be harder without the Gowin tool chain. I am not sure. Thanks for the comment.

Glad you found it helpful. I was attracted to the Tang Nano boards by their low cost. They are cheap enough to buy just to tinker with them and learn about FPGA development. I also like that they are bread board friendly. GAO is helpful, at least on Windows. The latest educational version is more stable.

@@electronics.tinker I only dug out my old Nano 1k board the other day. I bought it a few years back. I couldn't use the educational version - it no longer supported my device so I got in touch with Gowin. They replied to me very quickly and advised me to install the latest non-educational version. I had avoided the non-educational version thinking there would be an associated cost with the license but there doesn't appear to be.

I have read that the non-educational version is free, but you have to apply for a license (I think annually). I have been using the educational version just to avoid bothering with a license. Have you noticed any features missing from the educational version other than support for some devices? That would be interesting to know. Cheers.

@@electronics.tinker I haven't used it enough to notice, sorry. When you install the 'full' version, it replaces the educational one (on Windows) so I haven't been able to do a side-by-side comparison. I do switch between 3 PCs though and I've had no trouble getting licenses for all 3. They're pretty good with their support - definitely a game changer for people wanting to get into FPGA on a budget. My project got too large for the Cyclone IV - mainly because of the amount of logging I was doing with SignalTap, so that's what forced me into buying a Cyclone V - just for development. I'm sure the Tang 1k/4k/9k will suffice my needs - and to be honest, the 4K seems to be the same price as the 9k now. I think the only concern with these boards is the number of pins.. but the Tang Primer seems to have that covered. I think you can even swap out 25k chips on those Primer dev boards too which is quite exciting.

The analyzer oscilloscope works for me only on Windows, where I have found it to be useful on both the Tang Nano 9K and the Tang Nano 20K. Tools version 1.9.9.03 education is better than the older version. But I have never gotten the oscilloscope to work on Linux (Ubuntu 22.04.05). The loader/programmer is also problematic on Linux but works ok on Windows. In the end, better to use Windows for Gowin if you can.

@@electronics.tinker it is sad that it doesnt work on linux... as for the programmer i found out that openFPGALloader works fine with ubuntu (it is mentioned on their website as am alternative). I hope they make an alternayive to gao too. Their fpgas are nice and affordable, it would be great to work on linux too

My bet is that running Linux on PicoRV32 would not be possible unless you add support to Linux for the PicoRV32's non-standard interrupts. And then you would have to run MMU-less Linux which is possible but not a great idea in my opinion. And you would need at add support for the Gowin PSRAM to get enough memory. Running Linux on a larger soft core than PicoRV32 is probably possible on the Tang Nano 9K. See the litex project. I am 100% sure it is possible on the Tang Nano 20K, but even then I think it makes more sense on a hard RISC-V core that complies to the supervisor-level spec or a hard Cortex-A core. I don't know of a cheap FPGA with either, though. Connecting a Raspberry Pi Zero to a small Tang Nano board by something faster than i2c would be possible and interesting. Best wishes.

@@electronics.tinker thank you for your detailed response to my question!! I did look up the litex project. It says it is possible to be made on the 9k. Thank you for the information!!

Since I made this video, Gowin released version 1.9.9.03 of the educational version of their tools. GOA is less glitchy with this version. I have found it to be useful.

Nice.. I use linux and openFPGALoader. I set up the .rao file and burn the design. But when i try to open the oscilloscope i get the error : Can not connect to jtag server... Any idea why this happens? Iuse the tang primer 20K board

I figure this out (using chat gpt) i had to rename one file (libz.so.1 to libz.so.1.bak). Now i have another problem... i have made a simple counter 25 bits. After setting the clock(clk) and triger (ther reset signal assigned to button T10 of the board), when i press the auto button and then click the reset button on the board seems like it doesnt trigger anything...The only thing i made different was to select gowin usb cable GWU2K beacause the other option (there are only 2 for tang primer 20k i gwess) gave an error. Any idea why this happen? (i have downloaded the 1.9.9.03 version ). I have tried it many times... Seems like the analizer osc. software can not communicate with the board for some reason

I never got GAO to work on Linux. I think it is somewhat tied to an older version of Ubuntu than I have. You could use "ldd command" to see what shared libraries "command" will use. There are many shared libraries packaged with the Gowin tools on Linux, but maybe Gowin would be better off offering a Linux container or something. Making a program work on all flavors of Linux can be difficult. I prefer to develop on Linux, but I find that the Gowin tools work more smoothly on Windows.

Glad you liked it. My thought is that using software is only adding a little latency to reacting. The time measurement is already pure hardware. Given a 1 second measurement period from the GPS, I think a little added reaction latency will have little impact. It might help to run clk_pps faster to reduce measurement jitter, and using the PicoRV32 core makes that more difficult (at least until I can figure out how to do floor planning with the Gowin tools, perhaps).

@@electronics.tinker It might also be interesting to use the GPS PPS to discipline an external TCXO, instead of the onboard oscillator to reduce jitter. There is a project called the time card from the open compute project which does something similar, but IIRC it's implemented entirely in HDL.

I looked at Time Card. It mentions some interesting parts like a TCXO that has a PPS in signal. It looks like it can adjust itself. Interesting. Thanks for pointing out this project.

Apologies for the typo Grug

Yes, I can think of many variations to try, but I am not sure the result will be much better (although faster convergence is certainly possible). The big issue is that the GPS PPS signals are not perfect. I have two GPS receivers and I examined their PPS signals at the same time on my scope. The time between their rising edges varied by as much as 100 ns and was not constant. Maybe I should make a short video about this. A spec sheet from U-Blox suggests that the PPS signals might jitter less than 30ns (usually), but I don't know if this is true for what I have. I have no frequency reference adequate to test this. Someone who has one ought to make a video about using it to test cheap GPS modules! Thanks for your comment.

On the Tang Nano 9K, the project uses 37% of the available logic and 47% of the CLS's-- but a lot of that is the PicoRV32 core. I don't have a Tang Nano 4K (or 1K), but I think the 4K has a Cortex M3 hard core. You would have to use it instead of the PicoRV32 soft core. Then, I think there is a good chance it would work. The 1K is too small for the PicoRV32 core (and I think it has no ARM core). So, the only approach would be to use the 1K in conjunction with an external CPU like a Raspberry Pi, Arduino, or ESP32. You could use i2c to read and write the PPS registers. One other concern is speed. clk_pps should be at least 60 MHz. I am not sure what speeds the 1K and 4K would support. I have noticed that higher resource utilization causes the place and route tool to be less likely to achieve a given clock speed. I have no idea about the 1K and 4K in this regard. I also don't know how to use the floorplanner tool to help the place and route, but that's a topic for another day.

Thank you for the very kind comment. I enjoy these technologies and make videos in the hope that others will enjoy them also.

It's a fair point. Better to try it than just give up. Certainly, I have had success on breadboards way above 1 MHz.

Having a hard core on an FPGA would certainly be interesting. But the 4K is a fairly small FPGA. A Tang Nano 9K with a PicoRV32 soft core likely will have as many resources left over after including the soft core as the 4K has in the first place. But the m3 will likely be faster. The Tang Nano 20K is also nice. After including a PicoRV32 soft core, it will have more resources left over than even the 9K. I think if you are just learning about FPGAs without a specific project in mind (in particular one that needs a core), then the 9K and 20K are good choices. The prices don't appear to be that different. My Tang 20K was $25 from Amazon. That was a good deal. If I could buy a 4K for, say $10, I'd probably get one just to see exactly how the m3 is integrated, though. Basically, they are all good choices in one way or another. By the way, in case you didn't see them, I have several videos that show the use of the PicoRV32 soft core. I like using the version straight from github rather than using the encrypted IP block available directly in the Gowin IDE.

No. I looked at it but decided that using the picorv32 direct from its author's git (github.com/YosysHQ/picorv32) was so much more transparent. It works the same way on the Tang Nano 20K. See my video on PicoRV32 interrupts. The github for it supports both the 9K and the 20K. Best wishes.

I am happy to hear that you found the video useful.

It's a good question. In general, you have to dig through and understand technical documentation available on the Gowin website to answer this type of question. The FPGA on the 9K is a GW1NR-9 with speed (and temperature) grade C6/I5. I am looking at document "GW1NR series of FPGA Products Data Sheet", version DS117-3.0E. Its Table 3-21 answers the question saying the max valid CLKOUT from rPLL is 600 MHz (and the min is 3.125 MHz). The table also gives limits on intermediate clocks that are involved. A separate document "Gowin Clock User Guide UG286" explains those intermediate clocks and how they form CLKCOUT. It's not easy stuff, and there are many docs to shift though. And then, you need a design that can actually use a 600 MHz clock while still meeting setup and hold times. I doubt there is much you can do on the GW1NR at such a high speed. It's why you have to look at the timing report that the tools generate to see if your design meets timing. There are still many aspects of this that I cannot understand from Gowin's docs. But I know that red text in the timing report means "bad!" Good luck with you FPGA.

Glad you enjoyed it and good idea. I created repo called grug_misc_projects on github under user grughuhler. Let's see if UA-cam lets me post a link. github.com/grughuhler/grug_misc_projects

Thank you so much for uploading those files. I am working on an order to Digikey so I can attempt to recreate what you demonstrated. Would you please confirm the values of R11-R14 and C6-C9? The schematic says {R} and {C}. Thank you again for providing this content.

Yes, my mistake. I deleted the LTSpice parameter without adding a note. C=10nF and R=220 Ohms. Those values are interesting to play with. I am unsure how to best select them. I'll fix the picture on the github later.

I'm glad you found the video interesting. Best wishes with your experiment.

The FPGA on the Tang Nano 20K (and the 9K) is a digital only device so its output pins are either high or low-- so it can produce square waves but not (directly) sine waves. If all you want is a square wave clock generator, check out a part called si5351. John Hawkes made a youtube video about using one of these as an LO sine wave generator by filtering its output. The video is called "SI5351 Clock Gen as Radio Local Oscillator in Old Radios".

@@electronics.tinker Thank you for your reply. I check out Hawkes video. I put a low pass filter into the output from the Si5351a and that knocked everything down a bit. However, the signal was knocked down below 0 db. So now I think I have to amplify and filter the results of the amplifier as well. ... So it goes.

I agree that winding toroids would be the best way to get and tune inductors for RF filters. I suppose it would be interesting to see how well a breadboard RF filters could work at low frequencies like 1 MHz. One could compare its response to what a filter designer web site predicts. I'm glad you enjoyed the video.

Thank you. It's great to hear from someone in Germany.

Do you mean implement a RISC-V soft core from scratch? That would be a big job. And others have already done it. See the litex project or the PicoRV32 core. I made a whole series of videos about using the PicoRV32 RISC-V core to implement a simple SoC. There is a playlist called PicoRV32 on my channel. The videos contain links to github with complete projects including some simple software. There are multiple branches on the github as I added stuff from video to video.

I presume you mean that the stereo audio will carry I and Q data to be upconverted to RF using the Tayloe circuit-- like for a transmitter. I have not tried this, although it would be fun. Dan Tayloe's paper briefly describes how to do it. I put a link to that paper in my first video about the Tayloe mixer "Tayloe RF Mixer Demonstration...". Also, you could check out NA5Y's youtube channel, in particular his video "ESP32 Based SDR Transmitter - Part 2 Tayloe Encoder". He shows a schematic. Cheers,

I think the performance of both could be improved by using an additional clock. I was trying to keep it simple. Clock domain crossing is a good topic, though. In the past, I tried to get the Gowin tool chain to complain about bad domain crossing. No luck with that so far.